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Searched refs:REG_SC_BK4F_C0 (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
353 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_4K2K_2D_FHD_YUV()
354 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_4K2K_2D_FHD_YUV()
355 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_4K2K_2D_FHD_YUV()
697 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
698 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
699 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1041 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_4K2K_2D_4K2K_YUV()
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H A DMaxim_2D_FHD.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
353 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_FHD_2D_FHD_YUV()
354 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_FHD_2D_FHD_YUV()
355 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_60.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A Dhwreg_frc_map.h11031 #define REG_SC_BK4F_C0 (REG_SCALER_BASE+0x4FC0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
353 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_4K2K_2D_FHD_YUV()
354 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_4K2K_2D_FHD_YUV()
355 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_4K2K_2D_FHD_YUV()
697 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
698 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
699 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1041 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_4K2K_2D_4K2K_YUV()
[all …]
H A DMaxim_2D_FHD.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
353 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_FHD_2D_FHD_YUV()
354 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_FHD_2D_FHD_YUV()
355 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K2K_120.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_60.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaxim_ACT_4K0_5K.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_ACT_4K1K.c9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A Dhwreg_frc_map.h11031 #define REG_SC_BK4F_C0 (REG_SCALER_BASE+0x4FC0) macro