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Searched refs:REG_SC_BK4F_08 (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x0C, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
364 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x0C, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
708 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1052 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
364 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_60.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A Dhwreg_frc_map.h10847 #define REG_SC_BK4F_08 (REG_SCALER_BASE+0x4F08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x0C, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
364 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x0C, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
708 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1052 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
364 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K2K_120.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_60.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaxim_ACT_4K0_5K.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_ACT_4K1K.c20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2 in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A Dhwreg_frc_map.h10847 #define REG_SC_BK4F_08 (REG_SCALER_BASE+0x4F08) macro