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Searched refs:REG_SC_BK3B_44_L (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_dip.c169 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
932 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
939 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_dip.c188 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
951 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
958 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_dip.c191 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1090 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1097 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_dip.c189 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1088 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1095 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c189 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1173 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1180 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_dip.c344 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1319 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1326 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_dip.c313 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1295 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1302 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_dip.c315 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1297 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1304 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_dip.c193 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1208 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1215 SC_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c678 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1822 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1829 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c679 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1788 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1795 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c679 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1823 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1830 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c679 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3)); in Hal_SC_DWIN_set_422_cbcr_swap()
1788 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0)); in HAL_XC_DIP_SetDataFmt()
1795 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0))); in HAL_XC_DIP_SetDataFmt()
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dhwreg_sc.h11528 #define REG_SC_BK3B_44_L _PK_L_(0x3B, 0x44) macro