| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_dip.c | 381 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
1091 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1102 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1108 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1114 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1120 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1131 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, BIT(2), BIT(2)); in HAL_XC_DIP_MuxDispatch()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_dip.c | 400 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
1104 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1115 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1121 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1127 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1133 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1142 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, BIT(2), BIT(2)); in HAL_XC_DIP_MuxDispatch()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_dip.c | 538 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_dip.c | 536 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_dip.c | 536 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_dip.c | 691 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_dip.c | 660 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_dip.c | 662 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_dip.c | 569 SC_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_dip.c | 1054 DIP_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_dip.c | 1055 DIP_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_dip.c | 1055 DIP_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_dip.c | 1055 DIP_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/ |
| H A D | hwreg_sc.h | 11428 #define REG_SC_BK3B_12_L _PK_L_(0x3B, 0x12) macro
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