Home
last modified time | relevance | path

Searched refs:REG_SC_BK34_40_L (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_dip.c336 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
340 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
345 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_dip.c355 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
359 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
364 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_dip.c474 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
478 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
483 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_dip.c472 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
476 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
481 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c472 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
476 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
481 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_dip.c627 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
631 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
636 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_dip.c596 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
600 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
605 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_dip.c598 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
602 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
607 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_dip.c501 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
505 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
510 SC_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c986 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
990 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
995 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c987 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
991 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
996 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c987 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
991 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
996 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c987 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
991 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
996 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_dip.c1245 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
1249 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
1254 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_dip.c1297 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
1301 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
1306 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0)); in HAL_XC_DIP_SetFRC()
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dhwreg_sc.h10642 #define REG_SC_BK34_40_L _PK_L_(0x34, 0x40) macro