| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_dip.c | 377 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
1029 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1040 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1046 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1052 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1058 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1064 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1075 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, BIT(2), BIT(2)); in HAL_XC_DIP_MuxDispatch()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_dip.c | 396 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
1046 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1057 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1063 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1069 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1075 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1081 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, 0, BIT(2)); in HAL_XC_DIP_MuxDispatch()
1090 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, BIT(2), BIT(2)); in HAL_XC_DIP_MuxDispatch()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_dip.c | 534 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_dip.c | 532 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_dip.c | 532 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_dip.c | 687 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_dip.c | 656 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_dip.c | 658 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_dip.c | 565 SC_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_dip.c | 1050 DIP_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_dip.c | 1051 DIP_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_dip.c | 1051 DIP_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_dip.c | 1051 DIP_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_dip.c | 1286 DIP_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_dip.c | 1338 DIP_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) ); in Hal_SC_DWIN_set_input_vsync_inverse()
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| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/ |
| H A D | hwreg_sc.h | 10516 #define REG_SC_BK34_01_L _PK_L_(0x34, 0x01) macro
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