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Searched refs:REG_SC_BK1C_7E_L (Results 1 – 25 of 67) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/
H A Dmhal_pq.c830 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, pBuf[i], 0x01FF); //data[8:0] in _Hal_PQ_set_sram_ihc_crd_table()
831 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/ace/
H A Dmhal_ace.c805 while (SC_R2BYTE(0, REG_SC_BK1C_7E_L) & BIT(15)); in Hal_ACE_Set_IHC_SRAM()
808 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, pBuf[i], 0x03FF); //data in Hal_ACE_Set_IHC_SRAM()
810 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/ace/
H A Dmhal_ace.c1090 while (SC_R2BYTE(0, REG_SC_BK1C_7E_L) & BIT(15)); in Hal_ACE_Set_IHC_SRAM()
1093 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, pBuf[i], 0x03FF); //data in Hal_ACE_Set_IHC_SRAM()
1095 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/ace/
H A Dmhal_ace.c1122 while (SC_R2BYTE(0, REG_SC_BK1C_7E_L) & BIT(15)); in Hal_ACE_Set_IHC_SRAM()
1125 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, pBuf[i], 0x03FF); //data in Hal_ACE_Set_IHC_SRAM()
1127 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/ace/
H A Dmhal_ace.c1077 while (SC_R2BYTE(0, REG_SC_BK1C_7E_L) & BIT(15)); in Hal_ACE_Set_IHC_SRAM()
1080 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, pBuf[i], 0x03FF); //data in Hal_ACE_Set_IHC_SRAM()
1082 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/
H A Dmhal_ace.c1077 while (SC_R2BYTE(0, REG_SC_BK1C_7E_L) & BIT(15)); in Hal_ACE_Set_IHC_SRAM()
1080 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, pBuf[i], 0x03FF); //data in Hal_ACE_Set_IHC_SRAM()
1082 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/ace/
H A Dmhal_ace.c1146 while (SC_R2BYTE(0, REG_SC_BK1C_7E_L) & BIT(15)); in Hal_ACE_Set_IHC_SRAM()
1149 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, pBuf[i], 0x03FF); //data in Hal_ACE_Set_IHC_SRAM()
1151 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/ace/
H A Dmhal_ace.c1146 while (SC_R2BYTE(0, REG_SC_BK1C_7E_L) & BIT(15)); in Hal_ACE_Set_IHC_SRAM()
1149 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, pBuf[i], 0x03FF); //data in Hal_ACE_Set_IHC_SRAM()
1151 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/
H A Dmhal_pq.c714 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, pBuf[i], 0x01FF); //data[8:0] in _Hal_PQ_set_sram_ihc_crd_table()
715 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/ace/
H A Dmhal_ace.c1565 while (SC_R2BYTE(0, REG_SC_BK1C_7E_L) & BIT(15)); in Hal_ACE_Set_IHC_SRAM()
1568 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, pBuf[i], 0x03FF); //data in Hal_ACE_Set_IHC_SRAM()
1570 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/ace/
H A Dmhal_ace.c1565 while (SC_R2BYTE(0, REG_SC_BK1C_7E_L) & BIT(15)); in Hal_ACE_Set_IHC_SRAM()
1568 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, pBuf[i], 0x03FF); //data in Hal_ACE_Set_IHC_SRAM()
1570 SC_W2BYTEMSK(0, REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/
H A Dmhal_pq.c1149 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, pBuf[i], 0x01FF); //data[8:0] in _Hal_PQ_set_sram_ihc_crd_table()
1150 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/
H A Dmhal_pq.c1149 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, pBuf[i], 0x01FF); //data[8:0] in _Hal_PQ_set_sram_ihc_crd_table()
1150 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/
H A Dmhal_pq.c1149 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, pBuf[i], 0x01FF); //data[8:0] in _Hal_PQ_set_sram_ihc_crd_table()
1150 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/
H A Dmhal_pq.c1149 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, pBuf[i], 0x01FF); //data[8:0] in _Hal_PQ_set_sram_ihc_crd_table()
1150 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7E_L, BIT(15), BIT(15)); // io_w enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h5833 #define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h5833 #define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h5835 #define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h5835 #define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h5835 #define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h5833 #define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h5835 #define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h5833 #define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A Dhwreg_dlc.h5835 #define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/
H A Dhwreg_ace.h5833 #define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) macro

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