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Searched refs:REG_SC_BK1C_7C_L (Results 1 – 25 of 67) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/
H A Dmhal_pq.c824 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_ihc_crd_table()
825 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_ihc_crd_table()
833 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_ihc_crd_table()
902 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_ihc_crd_table()
919 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_ihc_crd_table()
930 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/
H A Dmhal_pq.c708 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_ihc_crd_table()
709 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_ihc_crd_table()
717 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_ihc_crd_table()
786 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_ihc_crd_table()
803 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_ihc_crd_table()
814 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/
H A Dmhal_pq.c1143 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_ihc_crd_table()
1144 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_ihc_crd_table()
1152 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_ihc_crd_table()
1221 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_ihc_crd_table()
1238 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_ihc_crd_table()
1249 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/
H A Dmhal_pq.c1143 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_ihc_crd_table()
1144 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_ihc_crd_table()
1152 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_ihc_crd_table()
1221 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_ihc_crd_table()
1238 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_ihc_crd_table()
1249 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/
H A Dmhal_pq.c1143 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_ihc_crd_table()
1144 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_ihc_crd_table()
1152 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_ihc_crd_table()
1221 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_ihc_crd_table()
1238 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_ihc_crd_table()
1249 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/
H A Dmhal_pq.c1143 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_ihc_crd_table()
1144 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_ihc_crd_table()
1152 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_ihc_crd_table()
1221 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_ihc_crd_table()
1238 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_ihc_crd_table()
1249 MApi_XC_W2BYTEMSK(REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/ace/
H A Dmhal_ace.c800 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
801 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
813 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/ace/
H A Dmhal_ace.c1085 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
1086 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
1098 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/ace/
H A Dmhal_ace.c1117 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
1118 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
1130 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/ace/
H A Dmhal_ace.c1072 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
1073 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
1085 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/
H A Dmhal_ace.c1072 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
1073 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
1085 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/ace/
H A Dmhal_ace.c1141 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
1142 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
1154 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/ace/
H A Dmhal_ace.c1141 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
1142 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
1154 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/ace/
H A Dmhal_ace.c1560 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
1561 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
1573 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/ace/
H A Dmhal_ace.c1560 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
1561 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
1573 SC_W2BYTEMSK(0, REG_SC_BK1C_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h5829 #define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h5829 #define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h5831 #define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h5831 #define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h5831 #define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h5829 #define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h5831 #define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h5829 #define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A Dhwreg_dlc.h5831 #define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/
H A Dhwreg_ace.h5829 #define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) macro

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