Home
last modified time | relevance | path

Searched refs:REG_SC_BK1C_79_L (Results 1 – 25 of 67) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/
H A Dmhal_pq.c764 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x03FF); // address[9:0] in Hal_PQ_set_sram_icc_crd_table()
787 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x03FF); // address[9:0] in Hal_PQ_get_sram_icc_crd_table()
788 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, BIT(15), BIT(15)); // io_R enable in Hal_PQ_get_sram_icc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/
H A Dmhal_pq.c578 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x01FF); // address[8:0] in _Hal_PQ_set_sram_icc_crd_table()
671 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x01FF); // address[8:0] in Hal_PQ_get_sram_icc_crd_table()
672 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, BIT(15), BIT(15)); // io_R enable in Hal_PQ_get_sram_icc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/
H A Dmhal_pq.c1013 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x01FF); // address[8:0] in _Hal_PQ_set_sram_icc_crd_table()
1106 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x01FF); // address[8:0] in Hal_PQ_get_sram_icc_crd_table()
1107 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, BIT(15), BIT(15)); // io_R enable in Hal_PQ_get_sram_icc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/
H A Dmhal_pq.c1013 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x01FF); // address[8:0] in _Hal_PQ_set_sram_icc_crd_table()
1106 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x01FF); // address[8:0] in Hal_PQ_get_sram_icc_crd_table()
1107 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, BIT(15), BIT(15)); // io_R enable in Hal_PQ_get_sram_icc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/
H A Dmhal_pq.c1013 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x01FF); // address[8:0] in _Hal_PQ_set_sram_icc_crd_table()
1106 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x01FF); // address[8:0] in Hal_PQ_get_sram_icc_crd_table()
1107 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, BIT(15), BIT(15)); // io_R enable in Hal_PQ_get_sram_icc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/
H A Dmhal_pq.c1013 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x01FF); // address[8:0] in _Hal_PQ_set_sram_icc_crd_table()
1106 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, i, 0x01FF); // address[8:0] in Hal_PQ_get_sram_icc_crd_table()
1107 MApi_XC_W2BYTEMSK(REG_SC_BK1C_79_L, BIT(15), BIT(15)); // io_R enable in Hal_PQ_get_sram_icc_crd_table()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/ace/
H A Dmhal_ace.c825 SC_W2BYTEMSK(0, REG_SC_BK1C_79_L, i, 0x03FF); // address in Hal_ACE_Set_ICC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/ace/
H A Dmhal_ace.c1110 SC_W2BYTEMSK(0, REG_SC_BK1C_79_L, i, 0x03FF); // address in Hal_ACE_Set_ICC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/ace/
H A Dmhal_ace.c1142 SC_W2BYTEMSK(0, REG_SC_BK1C_79_L, i, 0x03FF); // address in Hal_ACE_Set_ICC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/ace/
H A Dmhal_ace.c1097 SC_W2BYTEMSK(0, REG_SC_BK1C_79_L, i, 0x03FF); // address in Hal_ACE_Set_ICC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/
H A Dmhal_ace.c1097 SC_W2BYTEMSK(0, REG_SC_BK1C_79_L, i, 0x03FF); // address in Hal_ACE_Set_ICC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/ace/
H A Dmhal_ace.c1166 SC_W2BYTEMSK(0, REG_SC_BK1C_79_L, i, 0x03FF); // address in Hal_ACE_Set_ICC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/ace/
H A Dmhal_ace.c1166 SC_W2BYTEMSK(0, REG_SC_BK1C_79_L, i, 0x03FF); // address in Hal_ACE_Set_ICC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/ace/
H A Dmhal_ace.c1585 SC_W2BYTEMSK(0, REG_SC_BK1C_79_L, i, 0x03FF); // address in Hal_ACE_Set_ICC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/ace/
H A Dmhal_ace.c1585 SC_W2BYTEMSK(0, REG_SC_BK1C_79_L, i, 0x03FF); // address in Hal_ACE_Set_ICC_SRAM()
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h5823 #define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h5823 #define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h5825 #define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h5825 #define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h5825 #define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h5823 #define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h5825 #define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h5823 #define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A Dhwreg_dlc.h5825 #define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/
H A Dhwreg_ace.h5823 #define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) macro

123