| /utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/ |
| H A D | mhal_pq.c | 573 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_icc_crd_table()
574 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_icc_crd_table()
582 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_icc_crd_table()
650 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_icc_crd_table()
667 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_icc_crd_table()
678 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_icc_crd_table()
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| /utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/ |
| H A D | mhal_pq.c | 1008 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_icc_crd_table()
1009 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_icc_crd_table()
1017 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_icc_crd_table()
1085 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_icc_crd_table()
1102 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_icc_crd_table()
1113 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_icc_crd_table()
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| /utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/ |
| H A D | mhal_pq.c | 1008 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_icc_crd_table()
1009 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_icc_crd_table()
1017 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_icc_crd_table()
1085 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_icc_crd_table()
1102 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_icc_crd_table()
1113 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_icc_crd_table()
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| /utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/ |
| H A D | mhal_pq.c | 1008 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_icc_crd_table()
1009 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_icc_crd_table()
1017 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_icc_crd_table()
1085 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_icc_crd_table()
1102 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_icc_crd_table()
1113 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_icc_crd_table()
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| /utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/ |
| H A D | mhal_pq.c | 1008 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_icc_crd_table()
1009 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_icc_crd_table()
1017 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_icc_crd_table()
1085 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_icc_crd_table()
1102 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_PQ_get_sram_icc_crd_table()
1113 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_icc_crd_table()
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| /utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/ |
| H A D | mhal_pq.c | 756 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_set_sram_icc_crd_table()
769 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in Hal_PQ_set_sram_icc_crd_table()
783 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en disable in Hal_PQ_get_sram_icc_crd_table()
794 MApi_XC_W2BYTEMSK(REG_SC_BK1C_78_L, 0, BIT(0)); // io_en enable in Hal_PQ_get_sram_icc_crd_table()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/ace/ |
| H A D | mhal_ace.c | 819 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_ICC_SRAM()
831 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_ICC_SRAM()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/ace/ |
| H A D | mhal_ace.c | 1104 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_ICC_SRAM()
1116 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_ICC_SRAM()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/ace/ |
| H A D | mhal_ace.c | 1136 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_ICC_SRAM()
1148 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_ICC_SRAM()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/ace/ |
| H A D | mhal_ace.c | 1091 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_ICC_SRAM()
1103 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_ICC_SRAM()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/ |
| H A D | mhal_ace.c | 1091 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_ICC_SRAM()
1103 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_ICC_SRAM()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/ace/ |
| H A D | mhal_ace.c | 1160 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_ICC_SRAM()
1172 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_ICC_SRAM()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/ace/ |
| H A D | mhal_ace.c | 1160 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_ICC_SRAM()
1172 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_ICC_SRAM()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/ace/ |
| H A D | mhal_ace.c | 1579 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_ICC_SRAM()
1591 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_ICC_SRAM()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/ace/ |
| H A D | mhal_ace.c | 1579 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_ICC_SRAM()
1591 SC_W2BYTEMSK(0, REG_SC_BK1C_78_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_ICC_SRAM()
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| /utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/ |
| H A D | hwreg_wble.h | 5821 #define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/ |
| H A D | hwreg_ace.h | 5821 #define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/ |
| H A D | hwreg_dlc.h | 5823 #define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/ |
| H A D | hwreg_ace.h | 5823 #define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/ |
| H A D | hwreg_dlc.h | 5823 #define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/ |
| H A D | hwreg_wble.h | 5821 #define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/ |
| H A D | hwreg_dlc.h | 5823 #define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/ |
| H A D | hwreg_ace.h | 5821 #define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/ |
| H A D | hwreg_dlc.h | 5823 #define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/ |
| H A D | hwreg_ace.h | 5821 #define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) macro
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