Home
last modified time | relevance | path

Searched refs:REG_SC_BK18_7E_L (Results 1 – 25 of 70) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/pq/hal/k6lite/pq/
H A Dmhal_pq.c619 while (MApi_XC_R2BYTE(REG_SC_BK18_7E_L) & BIT(8)); in _Hal_PQ_set_sram_ihc_crd_table()
622 MApi_XC_W2BYTEMSK(REG_SC_BK18_7E_L, pBuf[i], 0x00FF); //data in _Hal_PQ_set_sram_ihc_crd_table()
624 MApi_XC_W2BYTEMSK(REG_SC_BK18_7E_L, BIT(8), BIT(8)); // io_w enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/kano/pq/
H A Dmhal_pq.c621 while (MApi_XC_R2BYTE(REG_SC_BK18_7E_L) & BIT(8)); in _Hal_PQ_set_sram_ihc_crd_table()
624 MApi_XC_W2BYTEMSK(REG_SC_BK18_7E_L, pBuf[i], 0x00FF); //data in _Hal_PQ_set_sram_ihc_crd_table()
626 MApi_XC_W2BYTEMSK(REG_SC_BK18_7E_L, BIT(8), BIT(8)); // io_w enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/k6/pq/
H A Dmhal_pq.c619 while (MApi_XC_R2BYTE(REG_SC_BK18_7E_L) & BIT(8)); in _Hal_PQ_set_sram_ihc_crd_table()
622 MApi_XC_W2BYTEMSK(REG_SC_BK18_7E_L, pBuf[i], 0x00FF); //data in _Hal_PQ_set_sram_ihc_crd_table()
624 MApi_XC_W2BYTEMSK(REG_SC_BK18_7E_L, BIT(8), BIT(8)); // io_w enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/curry/pq/
H A Dmhal_pq.c619 while (MApi_XC_R2BYTE(REG_SC_BK18_7E_L) & BIT(8)); in _Hal_PQ_set_sram_ihc_crd_table()
622 MApi_XC_W2BYTEMSK(REG_SC_BK18_7E_L, pBuf[i], 0x00FF); //data in _Hal_PQ_set_sram_ihc_crd_table()
624 MApi_XC_W2BYTEMSK(REG_SC_BK18_7E_L, BIT(8), BIT(8)); // io_w enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/ace/
H A Dmhal_ace.c583 while (SC_R2BYTE(0,REG_SC_BK18_7E_L) & BIT(8)); in Hal_ACE_Set_IHC_SRAM()
586 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, pBuf[i], 0x00FF); //data in Hal_ACE_Set_IHC_SRAM()
588 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, BIT(8), BIT(8)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/ace/
H A Dmhal_ace.c583 while (SC_R2BYTE(0,REG_SC_BK18_7E_L) & BIT(8)); in Hal_ACE_Set_IHC_SRAM()
586 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, pBuf[i], 0x00FF); //data in Hal_ACE_Set_IHC_SRAM()
588 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, BIT(8), BIT(8)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/
H A Dmhal_ace.c583 while (SC_R2BYTE(0,REG_SC_BK18_7E_L) & BIT(8)); in Hal_ACE_Set_IHC_SRAM()
586 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, pBuf[i], 0x00FF); //data in Hal_ACE_Set_IHC_SRAM()
588 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, BIT(8), BIT(8)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/ace/
H A Dmhal_ace.c583 while (SC_R2BYTE(0,REG_SC_BK18_7E_L) & BIT(8)); in Hal_ACE_Set_IHC_SRAM()
586 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, pBuf[i], 0x00FF); //data in Hal_ACE_Set_IHC_SRAM()
588 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, BIT(8), BIT(8)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/
H A Dmhal_ace.c661 while (SC_R2BYTE(0,REG_SC_BK18_7E_L) & BIT(8)); in Hal_ACE_Set_IHC_SRAM()
664 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, pBuf[i], 0x00FF); //data in Hal_ACE_Set_IHC_SRAM()
666 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, BIT(8), BIT(8)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/
H A Dmhal_ace.c661 while (SC_R2BYTE(0,REG_SC_BK18_7E_L) & BIT(8)); in Hal_ACE_Set_IHC_SRAM()
664 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, pBuf[i], 0x00FF); //data in Hal_ACE_Set_IHC_SRAM()
666 SC_W2BYTEMSK(0,REG_SC_BK18_7E_L, BIT(8), BIT(8)); // io_w enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DMaserati_Sub.c12893 { PQ_MAP_REG(REG_SC_BK18_7E_L), 0xFF, 0x00/*OFF*/,
H A DMaserati_Main.c114589 { PQ_MAP_REG(REG_SC_BK18_7E_L), 0xFF, 0x00/*OFF*/, },
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DMaserati_Sub.c12893 { PQ_MAP_REG(REG_SC_BK18_7E_L), 0xFF, 0x00/*OFF*/,
H A DMaserati_Main.c114149 { PQ_MAP_REG(REG_SC_BK18_7E_L), 0xFF, 0x00/*OFF*/, },
/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/include/
H A DMooney_Main.c61312 { PQ_MAP_REG(REG_SC_BK18_7E_L), 0xFF, 0x00/*OFF*/, },
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A DManhattan_Main.c155441 { PQ_MAP_REG(REG_SC_BK18_7E_L), 0xFF, 0x00/*OFF*/, },
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h4794 #define REG_SC_BK18_7E_L _PK_L_(0x18, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h4794 #define REG_SC_BK18_7E_L _PK_L_(0x18, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h4796 #define REG_SC_BK18_7E_L _PK_L_(0x18, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h4796 #define REG_SC_BK18_7E_L _PK_L_(0x18, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h4796 #define REG_SC_BK18_7E_L _PK_L_(0x18, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DMaxim_Main.c157935 { PQ_MAP_REG(REG_SC_BK18_7E_L), 0xFF, 0x00/*OFF*/, },
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h4794 #define REG_SC_BK18_7E_L _PK_L_(0x18, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h4796 #define REG_SC_BK18_7E_L _PK_L_(0x18, 0x7E) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h4794 #define REG_SC_BK18_7E_L _PK_L_(0x18, 0x7E) macro

123