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Searched refs:REG_SC_BK18_7C_L (Results 1 – 25 of 70) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/pq/hal/k6lite/pq/
H A Dmhal_pq.c614 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_ihc_crd_table()
615 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_ihc_crd_table()
627 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/kano/pq/
H A Dmhal_pq.c616 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_ihc_crd_table()
617 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_ihc_crd_table()
629 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/k6/pq/
H A Dmhal_pq.c614 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_ihc_crd_table()
615 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_ihc_crd_table()
627 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/curry/pq/
H A Dmhal_pq.c614 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, BIT(0), BIT(0)); // io_en disable in _Hal_PQ_set_sram_ihc_crd_table()
615 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in _Hal_PQ_set_sram_ihc_crd_table()
627 MApi_XC_W2BYTEMSK(REG_SC_BK18_7C_L, 0, BIT(0)); // io_en enable in _Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/ace/
H A Dmhal_ace.c578 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, BIT(0), BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
579 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
591 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, 0, BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/ace/
H A Dmhal_ace.c578 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, BIT(0), BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
579 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
591 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, 0, BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/
H A Dmhal_ace.c578 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, BIT(0), BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
579 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
591 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, 0, BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/ace/
H A Dmhal_ace.c578 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, BIT(0), BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
579 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
591 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, 0, BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/
H A Dmhal_ace.c656 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
657 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
669 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/
H A Dmhal_ace.c656 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, BIT(0), BIT(0)); // io_en enable in Hal_ACE_Set_IHC_SRAM()
657 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select in Hal_ACE_Set_IHC_SRAM()
669 SC_W2BYTEMSK(0,REG_SC_BK18_7C_L, 0, BIT(0)); // io_en disable in Hal_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DMaserati_Sub.c12842 { PQ_MAP_REG(REG_SC_BK18_7C_L), 0xFF, 0x00/*OFF*/,
H A DMaserati_Main.c114587 { PQ_MAP_REG(REG_SC_BK18_7C_L), 0xFF, 0x00/*OFF*/, },
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DMaserati_Sub.c12842 { PQ_MAP_REG(REG_SC_BK18_7C_L), 0xFF, 0x00/*OFF*/,
H A DMaserati_Main.c114147 { PQ_MAP_REG(REG_SC_BK18_7C_L), 0xFF, 0x00/*OFF*/, },
/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/include/
H A DMooney_Main.c61310 { PQ_MAP_REG(REG_SC_BK18_7C_L), 0xFF, 0x00/*OFF*/, },
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A DManhattan_Main.c155439 { PQ_MAP_REG(REG_SC_BK18_7C_L), 0xFF, 0x00/*OFF*/, },
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h4790 #define REG_SC_BK18_7C_L _PK_L_(0x18, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h4790 #define REG_SC_BK18_7C_L _PK_L_(0x18, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h4792 #define REG_SC_BK18_7C_L _PK_L_(0x18, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h4792 #define REG_SC_BK18_7C_L _PK_L_(0x18, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h4792 #define REG_SC_BK18_7C_L _PK_L_(0x18, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DMaxim_Main.c157933 { PQ_MAP_REG(REG_SC_BK18_7C_L), 0xFF, 0x00/*OFF*/, },
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h4790 #define REG_SC_BK18_7C_L _PK_L_(0x18, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h4792 #define REG_SC_BK18_7C_L _PK_L_(0x18, 0x7C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h4790 #define REG_SC_BK18_7C_L _PK_L_(0x18, 0x7C) macro

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