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Searched refs:REG_SC_BK02_73_L (Results 1 – 25 of 63) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/
H A Dmhal_pq_adaptive.c2000 reg.HDSDD_underflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x003F) ); in MDrv_SC_SaveHpfSetting()
2001 reg.HDSDD_overflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x3F00) >> 8 ); in MDrv_SC_SaveHpfSetting()
2020 MS_U8 HDSDD_underflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x003F) );
2021 MS_U8 HDSDD_overflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x3F00) >> 8 );
2060 …MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x0000, 0x003F); /* underflow */ //Reset for Full range in Mas… in MDrv_SC_hpfDefaultRelod()
2061 …MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3F00, 0x3F00); /* overflow *///Reset for Full range in Maser… in MDrv_SC_hpfDefaultRelod()
2071 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x000C, 0x003F); /* underflow */ in MDrv_SC_hpfDefaultRelod()
2072 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3200, 0x3F00); /* overflow */ in MDrv_SC_hpfDefaultRelod()
7865 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x0000 , 0x003F); /* underflow */ in MDrv_SC_hpfTolerantReport()
7866 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3F00, 0x3F00); /* overflow */ in MDrv_SC_hpfTolerantReport()
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/
H A Dmhal_pq_adaptive.c2000 reg.HDSDD_underflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x003F) ); in MDrv_SC_SaveHpfSetting()
2001 reg.HDSDD_overflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x3F00) >> 8 ); in MDrv_SC_SaveHpfSetting()
2020 MS_U8 HDSDD_underflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x003F) );
2021 MS_U8 HDSDD_overflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x3F00) >> 8 );
2060 …MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x0000, 0x003F); /* underflow */ //Reset for Full range in Mas… in MDrv_SC_hpfDefaultRelod()
2061 …MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3F00, 0x3F00); /* overflow *///Reset for Full range in Maser… in MDrv_SC_hpfDefaultRelod()
2071 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x000C, 0x003F); /* underflow */ in MDrv_SC_hpfDefaultRelod()
2072 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3200, 0x3F00); /* overflow */ in MDrv_SC_hpfDefaultRelod()
7865 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x0000 , 0x003F); /* underflow */ in MDrv_SC_hpfTolerantReport()
7866 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3F00, 0x3F00); /* overflow */ in MDrv_SC_hpfTolerantReport()
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/
H A Dmhal_pq_adaptive.c2000 reg.HDSDD_underflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x003F) ); in MDrv_SC_SaveHpfSetting()
2001 reg.HDSDD_overflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x3F00) >> 8 ); in MDrv_SC_SaveHpfSetting()
2020 MS_U8 HDSDD_underflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x003F) );
2021 MS_U8 HDSDD_overflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x3F00) >> 8 );
2060 …MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x0000, 0x003F); /* underflow */ //Reset for Full range in Mas… in MDrv_SC_hpfDefaultRelod()
2061 …MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3F00, 0x3F00); /* overflow *///Reset for Full range in Maser… in MDrv_SC_hpfDefaultRelod()
2071 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x000C, 0x003F); /* underflow */ in MDrv_SC_hpfDefaultRelod()
2072 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3200, 0x3F00); /* overflow */ in MDrv_SC_hpfDefaultRelod()
7865 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x0000 , 0x003F); /* underflow */ in MDrv_SC_hpfTolerantReport()
7866 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3F00, 0x3F00); /* overflow */ in MDrv_SC_hpfTolerantReport()
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/
H A Dmhal_pq_adaptive.c2000 reg.HDSDD_underflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x003F) ); in MDrv_SC_SaveHpfSetting()
2001 reg.HDSDD_overflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x3F00) >> 8 ); in MDrv_SC_SaveHpfSetting()
2020 MS_U8 HDSDD_underflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x003F) );
2021 MS_U8 HDSDD_overflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x3F00) >> 8 );
2060 …MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x0000, 0x003F); /* underflow */ //Reset for Full range in Mas… in MDrv_SC_hpfDefaultRelod()
2061 …MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3F00, 0x3F00); /* overflow *///Reset for Full range in Maser… in MDrv_SC_hpfDefaultRelod()
2071 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x000C, 0x003F); /* underflow */ in MDrv_SC_hpfDefaultRelod()
2072 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3200, 0x3F00); /* overflow */ in MDrv_SC_hpfDefaultRelod()
7865 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x0000 , 0x003F); /* underflow */ in MDrv_SC_hpfTolerantReport()
7866 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3F00, 0x3F00); /* overflow */ in MDrv_SC_hpfTolerantReport()
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/
H A Dmhal_pq_adaptive.c2013 reg.HDSDD_underflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x003F) ); in MDrv_SC_SaveHpfSetting()
2014 reg.HDSDD_overflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x3F00) >> 8 ); in MDrv_SC_SaveHpfSetting()
2033 MS_U8 HDSDD_underflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x003F) );
2034 MS_U8 HDSDD_overflow_threshold = (MS_U8)( MApi_XC_R2BYTEMSK(REG_SC_BK02_73_L, 0x3F00) >> 8 );
2072 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x000C, 0x003F); /* underflow */ in MDrv_SC_hpfDefaultRelod()
2073 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3200, 0x3F00); /* overflow */ in MDrv_SC_hpfDefaultRelod()
7832 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x0000 , 0x003F); /* underflow */ in MDrv_SC_hpfTolerantReport()
7833 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3F00, 0x3F00); /* overflow */ in MDrv_SC_hpfTolerantReport()
8071 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x000C, 0x003F); /* underflow */ in MDrv_SC_SDHD_FilterOneReport()
8072 MApi_XC_W2BYTEMSK(REG_SC_BK02_73_L, 0x3200, 0x3F00); /* overflow */ in MDrv_SC_SDHD_FilterOneReport()
/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/include/
H A DMooney_Main.c2452 { PQ_MAP_REG(REG_SC_BK02_73_L), 0x3F, 0x00/*OFF*/,
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DMaserati_Main.c2688 { PQ_MAP_REG(REG_SC_BK02_73_L), 0x3F, 0x0C/*OFF*/,
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DMaserati_Main.c5064 { PQ_MAP_REG(REG_SC_BK02_73_L), 0x3F, 0x0C/*OFF*/,
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A DManhattan_Main.c2627 { PQ_MAP_REG(REG_SC_BK02_73_L), 0x3F, 0x0C/*OFF*/,
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h861 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h861 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h863 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h861 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h863 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DMaxim_Main.c5065 { PQ_MAP_REG(REG_SC_BK02_73_L), 0x3F, 0x0C/*OFF*/,
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h861 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h863 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h861 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A Dhwreg_dlc.h863 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/
H A Dhwreg_ace.h861 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/messi/dlc/include/
H A Dhwreg_dlc.h863 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/messi/wble/include/
H A Dhwreg_wble.h861 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/M7821/wble/include/
H A Dhwreg_wble.h861 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/ace/include/
H A Dhwreg_ace.h861 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/maxim/wble/include/
H A Dhwreg_wble.h861 #define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) macro

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