Home
last modified time | relevance | path

Searched refs:REG_RTC_CTRL_REG (Results 1 – 25 of 30) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/rtc/hal/maldives/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
313 HAL_RTC_Write2Byte(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG, 0x0000); in HAL_RTC_ClearCTRL()
/utopia/UTPA2-700.0.x/modules/rtc/hal/mustang/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
313 HAL_RTC_Write2Byte(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG, 0x0000); in HAL_RTC_ClearCTRL()
/utopia/UTPA2-700.0.x/modules/rtc/hal/maxim/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
H A DregRTC.h112 #define REG_RTC_CTRL_REG (0x0000UL) macro
/utopia/UTPA2-700.0.x/modules/rtc/hal/macan/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
H A DregRTC.h112 #define REG_RTC_CTRL_REG (0x0000UL) macro
/utopia/UTPA2-700.0.x/modules/rtc/hal/kano/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
/utopia/UTPA2-700.0.x/modules/rtc/hal/k6lite/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
/utopia/UTPA2-700.0.x/modules/rtc/hal/maserati/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
H A DregRTC.h112 #define REG_RTC_CTRL_REG (0x0000UL) macro
/utopia/UTPA2-700.0.x/modules/rtc/hal/M7821/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
H A DregRTC.h112 #define REG_RTC_CTRL_REG (0x0000UL) macro
/utopia/UTPA2-700.0.x/modules/rtc/hal/messi/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
H A DregRTC.h112 #define REG_RTC_CTRL_REG (0x0000UL) macro
/utopia/UTPA2-700.0.x/modules/rtc/hal/k6/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
H A DregRTC.h112 #define REG_RTC_CTRL_REG (0x0000UL) macro
/utopia/UTPA2-700.0.x/modules/rtc/hal/curry/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
/utopia/UTPA2-700.0.x/modules/rtc/hal/mainz/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
H A DregRTC.h112 #define REG_RTC_CTRL_REG (0x0000UL) macro
/utopia/UTPA2-700.0.x/modules/rtc/hal/mooney/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
H A DregRTC.h112 #define REG_RTC_CTRL_REG (0x0000UL) macro
/utopia/UTPA2-700.0.x/modules/rtc/hal/manhattan/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
H A DregRTC.h112 #define REG_RTC_CTRL_REG (0x0000UL) macro
/utopia/UTPA2-700.0.x/modules/rtc/hal/M7621/rtc/
H A DhalRTC.c242 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_SOFT_RSTZ_BIT,bEnable); in HAL_RTC_RESET()
247 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_CNT_EN_BIT,bEnable); in HAL_RTC_Counter()
252 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_WRAP_EN_BIT,bEnable); in HAL_RTC_Wrap_Count()
257 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_LOAD_EN_BIT,bEnable); in HAL_RTC_Loading()
262 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_READ_EN_BIT,bEnable); in HAL_RTC_Reading()
267 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_MASK_BIT,bEnable); in HAL_RTC_IntMask()
272 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_FORCE_BIT,ENABLE); in HAL_RTC_IntForce()
277 HAL_RTC_WriteBit(HAL_RTC_GET_BASE(eRtc)+REG_RTC_CTRL_REG,RTC_INT_CLEAR_BIT,ENABLE); in HAL_RTC_IntClear()
H A DregRTC.h112 #define REG_RTC_CTRL_REG (0x0000UL) macro

12