Searched refs:REG_R2_1_CTRL_BASE (Results 1 – 16 of 16) sorted by relevance
171 #define REG_R2_1_CTRL_BASE 0x112900 macro173 #define REG_R2_1_CTRL REG_R2_1_CTRL_BASE+0x80519 tmp_H = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x12); in HAL_DEC_R2_SetCommInfo()520 tmp_L = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x10); in HAL_DEC_R2_SetCommInfo()626 tmp_H = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x12); in HAL_DEC_R2_GetCommInfo()627 tmp_L = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x10); in HAL_DEC_R2_GetCommInfo()
168 #define REG_R2_1_CTRL_BASE 0x112900 macro170 #define REG_R2_1_CTRL REG_R2_1_CTRL_BASE+0x80516 tmp_H = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x12); in HAL_DEC_R2_SetCommInfo()517 tmp_L = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x10); in HAL_DEC_R2_SetCommInfo()623 tmp_H = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x12); in HAL_DEC_R2_GetCommInfo()624 tmp_L = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x10); in HAL_DEC_R2_GetCommInfo()
149 #define REG_R2_1_CTRL_BASE 0x163000 macro151 #define REG_R2_1_CTRL REG_R2_1_CTRL_BASE+0x80538 tmp_H = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x12); in HAL_DEC_R2_SetCommInfo()539 tmp_L = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x10); in HAL_DEC_R2_SetCommInfo()645 tmp_H = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x12); in HAL_DEC_R2_GetCommInfo()646 tmp_L = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x10); in HAL_DEC_R2_GetCommInfo()
480 tmp_H = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x12); in HAL_DEC_R2_SetCommInfo()481 tmp_L = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x10); in HAL_DEC_R2_SetCommInfo()587 tmp_H = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x12); in HAL_DEC_R2_GetCommInfo()588 tmp_L = HAL_AUR2_ReadReg(REG_R2_1_CTRL_BASE+0x10); in HAL_DEC_R2_GetCommInfo()
833 #define REG_R2_1_CTRL_BASE 0x112900 macro835 #define REG_R2_1_CTRL REG_R2_1_CTRL_BASE+0x80
720 #define REG_R2_1_CTRL_BASE 0x112900 macro722 #define REG_R2_1_CTRL REG_R2_1_CTRL_BASE+0x80
278 HAL_AUR2_WriteMaskByte((REG_R2_1_CTRL_BASE + 0x40), 0xFF, 0x10); in HAL_DEC_R2_EnableR2()
726 #define REG_R2_1_CTRL_BASE 0x112900 macro728 #define REG_R2_1_CTRL REG_R2_1_CTRL_BASE+0x80
748 #define REG_R2_1_CTRL_BASE 0x163000 macro760 #define REG_SNDR2_CTRL_BASE (REG_R2_1_CTRL_BASE)
752 #define REG_R2_1_CTRL_BASE 0x163000 macro764 #define REG_SNDR2_CTRL_BASE (REG_R2_1_CTRL_BASE)
148 #define REG_R2_1_CTRL_BASE 0x163000 macro150 #define REG_R2_1_CTRL REG_R2_1_CTRL_BASE+0x80
173 #define REG_R2_1_CTRL_BASE 0x113000 macro175 #define REG_R2_1_CTRL REG_R2_1_CTRL_BASE+0x80
149 #define REG_R2_1_CTRL_BASE 0x163000 macro151 #define REG_R2_1_CTRL REG_R2_1_CTRL_BASE+0x80
143 #define REG_R2_1_CTRL_BASE 0x163000 macro145 #define REG_R2_1_CTRL REG_R2_1_CTRL_BASE+0x80