Searched refs:REG_R2_0_CTRL_BASE (Results 1 – 16 of 16) sorted by relevance
157 #define REG_R2_0_CTRL_BASE 0x112900 macro159 #define REG_R2_0_CTRL REG_R2_0_CTRL_BASE+0x80472 tmp_H = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x12); in HAL_SND_R2_SetCommInfo()473 tmp_L = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x10); in HAL_SND_R2_SetCommInfo()576 tmp_H = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x12); in HAL_SND_R2_GetCommInfo()577 tmp_L = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x10); in HAL_SND_R2_GetCommInfo()
154 #define REG_R2_0_CTRL_BASE 0x112900 macro156 #define REG_R2_0_CTRL REG_R2_0_CTRL_BASE+0x80469 tmp_H = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x12); in HAL_SND_R2_SetCommInfo()470 tmp_L = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x10); in HAL_SND_R2_SetCommInfo()573 tmp_H = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x12); in HAL_SND_R2_GetCommInfo()574 tmp_L = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x10); in HAL_SND_R2_GetCommInfo()
136 #define REG_R2_0_CTRL_BASE 0x112900 macro138 #define REG_R2_0_CTRL REG_R2_0_CTRL_BASE+0x80491 tmp_H = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x12); in HAL_SND_R2_SetCommInfo()492 tmp_L = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x10); in HAL_SND_R2_SetCommInfo()595 tmp_H = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x12); in HAL_SND_R2_GetCommInfo()596 tmp_L = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x10); in HAL_SND_R2_GetCommInfo()
433 tmp_H = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x12); in HAL_SND_R2_SetCommInfo()434 tmp_L = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x10); in HAL_SND_R2_SetCommInfo()537 tmp_H = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x12); in HAL_SND_R2_GetCommInfo()538 tmp_L = HAL_AUR2_ReadReg(REG_R2_0_CTRL_BASE+0x10); in HAL_SND_R2_GetCommInfo()
820 #define REG_R2_0_CTRL_BASE 0x112900 macro822 #define REG_R2_0_CTRL REG_R2_0_CTRL_BASE+0x80
734 #define REG_R2_0_CTRL_BASE 0x163000 macro736 #define REG_R2_0_CTRL REG_R2_0_CTRL_BASE+0x80
263 HAL_AUR2_WriteMaskByte((REG_R2_0_CTRL_BASE + 0x40), 0xFF, 0x10); in HAL_SND_R2_EnableR2()
740 #define REG_R2_0_CTRL_BASE 0x163000 macro742 #define REG_R2_0_CTRL REG_R2_0_CTRL_BASE+0x80
743 #define REG_R2_0_CTRL_BASE 0x112900 macro754 #define REG_DECR2_CTRL_BASE (REG_R2_0_CTRL_BASE)
747 #define REG_R2_0_CTRL_BASE 0x112900 macro758 #define REG_DECR2_CTRL_BASE (REG_R2_0_CTRL_BASE)
136 #define REG_R2_0_CTRL_BASE 0x112900 macro138 #define REG_R2_0_CTRL REG_R2_0_CTRL_BASE+0x80
161 #define REG_R2_0_CTRL_BASE 0x112900 macro163 #define REG_R2_0_CTRL REG_R2_0_CTRL_BASE+0x80
137 #define REG_R2_0_CTRL_BASE 0x112900 macro139 #define REG_R2_0_CTRL REG_R2_0_CTRL_BASE+0x80
131 #define REG_R2_0_CTRL_BASE 0x112900 macro133 #define REG_R2_0_CTRL REG_R2_0_CTRL_BASE+0x80