| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_mux.c | 333 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(0), BMASK(3:0)); // MHL3 ATOP Port-0 enable in Hal_SC_mux_set_dvi_mux()
334 W2BYTEMSK(REG_PM_SLEEP_4D_L, 0, BMASK(5:4)); // reg_hdcp_scdc_sel => DDCDA in Hal_SC_mux_set_dvi_mux()
356 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(1), BMASK(3:0)); // MHL3 ATOP Port-1 enable in Hal_SC_mux_set_dvi_mux()
357 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(4), BMASK(5:4)); // reg_hdcp_scdc_sel => DDCDB in Hal_SC_mux_set_dvi_mux()
379 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(2), BMASK(3:0)); // MHL3 ATOP Port-2 enable in Hal_SC_mux_set_dvi_mux()
380 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(5), BMASK(5:4)); // reg_hdcp_scdc_sel => DDCDC in Hal_SC_mux_set_dvi_mux()
402 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(3), BMASK(3:0)); // MHL3 ATOP Port-3 enable in Hal_SC_mux_set_dvi_mux()
403 W2BYTEMSK(REG_PM_SLEEP_4D_L, BMASK(5:4), BMASK(5:4)); // reg_hdcp_scdc_sel => DDCDD in Hal_SC_mux_set_dvi_mux()
425 W2BYTEMSK(REG_PM_SLEEP_4D_L, 0, BMASK(3:0)); // MHL3 ATOP Port-0/1/2/3 disable in Hal_SC_mux_set_dvi_mux()
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| H A D | mhal_hdmi.c | 208 MS_U8 ucDVIMuxSelect = R2BYTE(REG_PM_SLEEP_4D_L) &BMASK(3:0); in _Hal_tmds_CheckPortSelectMux0()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_mux.c | 333 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(0), BMASK(3:0)); // MHL3 ATOP Port-0 enable in Hal_SC_mux_set_dvi_mux()
334 W2BYTEMSK(REG_PM_SLEEP_4D_L, 0, BMASK(5:4)); // reg_hdcp_scdc_sel => DDCDA in Hal_SC_mux_set_dvi_mux()
357 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(1), BMASK(3:0)); // MHL3 ATOP Port-1 enable in Hal_SC_mux_set_dvi_mux()
358 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(4), BMASK(5:4)); // reg_hdcp_scdc_sel => DDCDB in Hal_SC_mux_set_dvi_mux()
381 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(2), BMASK(3:0)); // MHL3 ATOP Port-2 enable in Hal_SC_mux_set_dvi_mux()
382 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(5), BMASK(5:4)); // reg_hdcp_scdc_sel => DDCDC in Hal_SC_mux_set_dvi_mux()
405 W2BYTEMSK(REG_PM_SLEEP_4D_L, BIT(3), BMASK(3:0)); // MHL3 ATOP Port-3 enable in Hal_SC_mux_set_dvi_mux()
406 W2BYTEMSK(REG_PM_SLEEP_4D_L, BMASK(5:4), BMASK(5:4)); // reg_hdcp_scdc_sel => DDCDD in Hal_SC_mux_set_dvi_mux()
429 W2BYTEMSK(REG_PM_SLEEP_4D_L, 0, BMASK(3:0)); // MHL3 ATOP Port-0/1/2/3 disable in Hal_SC_mux_set_dvi_mux()
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| H A D | mhal_hdmi.c | 210 MS_U8 ucDVIMuxSelect = R2BYTE(REG_PM_SLEEP_4D_L) &BMASK(3:0); in _Hal_tmds_CheckPortSelectMux0()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_pm_sleep.h | 255 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_pm_sleep.h | 256 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_pm_sleep.h | 256 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_pm_sleep.h | 255 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_pm_sleep.h | 255 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_pm_sleep.h | 255 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_pm_sleep.h | 256 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_pm_sleep.h | 255 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_pm_sleep.h | 255 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_pm_sleep.h | 256 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_pm_sleep.h | 256 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_pm_sleep.h | 255 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_pm_sleep.h | 256 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_pm_sleep.h | 255 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_pm_sleep.h | 255 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/ |
| H A D | halMHL.c | 1812 return (R2BYTE(REG_PM_SLEEP_4D_L) &BMASK(2:0)); in mhal_mhl_GetInputPort()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/ |
| H A D | halMHL.c | 1812 return (R2BYTE(REG_PM_SLEEP_4D_L) &BMASK(2:0)); in mhal_mhl_GetInputPort()
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