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Searched refs:REG_MBX_BASE (Results 1 – 25 of 51) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h232 #define REG_MBX_BASE (0x63400) macro
238 #define REG_MBX_BASE (0x0400) macro
326 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
328 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
329 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
330 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
331 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
333 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
337 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
344 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h232 #define REG_MBX_BASE (0x63400) macro
238 #define REG_MBX_BASE (0x0400) macro
334 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
336 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
337 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
338 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
339 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
341 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
345 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
352 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h232 #define REG_MBX_BASE (0x63400) macro
238 #define REG_MBX_BASE (0x0400) macro
334 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
336 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
337 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
338 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
339 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
341 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
345 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
352 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h232 #define REG_MBX_BASE (0x63400) macro
238 #define REG_MBX_BASE (0x0400) macro
334 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
336 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
337 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
338 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
339 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
341 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
345 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
352 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h232 #define REG_MBX_BASE (0x63400) macro
238 #define REG_MBX_BASE (0x0400) macro
334 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
336 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
337 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
338 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
339 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
341 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
345 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
352 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h232 #define REG_MBX_BASE (0x63400) macro
238 #define REG_MBX_BASE (0x0400) macro
334 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
336 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
337 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
338 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
339 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
341 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
345 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
352 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h232 #define REG_MBX_BASE (0x63400) macro
238 #define REG_MBX_BASE (0x0400) macro
334 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
336 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
337 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
338 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
339 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
341 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
345 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
352 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h232 #define REG_MBX_BASE (0x63400) macro
238 #define REG_MBX_BASE (0x0400) macro
334 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
336 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
337 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
338 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
339 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
341 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
345 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
352 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h232 #define REG_MBX_BASE (0x63400) macro
238 #define REG_MBX_BASE (0x0400) macro
334 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
336 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
337 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
338 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
339 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
341 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
345 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
352 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DregVPU.h230 #define REG_MBX_BASE (0x0400) macro
294 #define VPU_REG_VERSION ( REG_MBX_BASE+(0x0055<<1))
295 #define VPU_REG_HI_MBOX0_L ( REG_MBX_BASE+(0x005b<<1))
296 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+( 0x005c<<1))
297 #define VPU_REG_HI_MBOX1_L ( REG_MBX_BASE+(0x005d<<1))
298 #define VPU_REG_HI_MBOX1_H ( REG_MBX_BASE+(0x005e<<1))
299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1))
302 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+( 0x0067<<1))
308 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
312 #define VPU_REG_HI_MBOX_RDY ( REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A DregVPU_EX.h230 #define REG_MBX_BASE (0x0400UL) macro
295 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
297 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
298 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
299 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
300 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
306 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
313 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
318 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DregVPU.h230 #define REG_MBX_BASE (0x0400) macro
294 #define VPU_REG_VERSION ( REG_MBX_BASE+(0x0055<<1))
295 #define VPU_REG_HI_MBOX0_L ( REG_MBX_BASE+(0x005b<<1))
296 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+( 0x005c<<1))
297 #define VPU_REG_HI_MBOX1_L ( REG_MBX_BASE+(0x005d<<1))
298 #define VPU_REG_HI_MBOX1_H ( REG_MBX_BASE+(0x005e<<1))
299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1))
302 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+( 0x0067<<1))
308 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
312 #define VPU_REG_HI_MBOX_RDY ( REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A DregVPU_EX.h230 #define REG_MBX_BASE (0x0400UL) macro
295 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
297 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
298 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
299 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
300 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
306 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
313 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
318 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A DregVPU_EX.h230 #define REG_MBX_BASE (0x0400UL) macro
295 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
297 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
298 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
299 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
300 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
306 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
313 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
318 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A DregVPU_EX.h230 #define REG_MBX_BASE (0x0400UL) macro
295 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
297 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
298 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
299 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
300 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
306 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
313 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
318 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DregVPU.h230 #define REG_MBX_BASE (0x0400) macro
294 #define VPU_REG_VERSION ( REG_MBX_BASE+(0x0055<<1))
295 #define VPU_REG_HI_MBOX0_L ( REG_MBX_BASE+(0x005b<<1))
296 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+( 0x005c<<1))
297 #define VPU_REG_HI_MBOX1_L ( REG_MBX_BASE+(0x005d<<1))
298 #define VPU_REG_HI_MBOX1_H ( REG_MBX_BASE+(0x005e<<1))
299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1))
302 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+( 0x0067<<1))
308 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
312 #define VPU_REG_HI_MBOX_RDY ( REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A DregVPU_EX.h230 #define REG_MBX_BASE (0x0400UL) macro
295 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
297 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
298 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
299 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
300 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
306 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
313 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
318 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/vpu_ex/
H A DregVPU_EX.h230 #define REG_MBX_BASE (0x0400UL) macro
295 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
297 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
298 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
299 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
300 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
306 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
313 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
318 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/vpu_ex/
H A DregVPU_EX.h230 #define REG_MBX_BASE (0x0400UL) macro
295 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
297 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
298 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
299 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
300 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
306 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
313 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
318 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/vpu/
H A DregVPU.h230 #define REG_MBX_BASE (0x0400) macro
294 #define VPU_REG_VERSION ( REG_MBX_BASE+(0x0055<<1))
295 #define VPU_REG_HI_MBOX0_L ( REG_MBX_BASE+(0x005b<<1))
296 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+( 0x005c<<1))
297 #define VPU_REG_HI_MBOX1_L ( REG_MBX_BASE+(0x005d<<1))
298 #define VPU_REG_HI_MBOX1_H ( REG_MBX_BASE+(0x005e<<1))
299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1))
302 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+( 0x0067<<1))
308 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
312 #define VPU_REG_HI_MBOX_RDY ( REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/vpu/
H A DregVPU.h230 #define REG_MBX_BASE (0x0400) macro
294 #define VPU_REG_VERSION ( REG_MBX_BASE+(0x0055<<1))
295 #define VPU_REG_HI_MBOX0_L ( REG_MBX_BASE+(0x005b<<1))
296 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+( 0x005c<<1))
297 #define VPU_REG_HI_MBOX1_L ( REG_MBX_BASE+(0x005d<<1))
298 #define VPU_REG_HI_MBOX1_H ( REG_MBX_BASE+(0x005e<<1))
299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1))
302 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+( 0x0067<<1))
308 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
312 #define VPU_REG_HI_MBOX_RDY ( REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/vpu/
H A DregVPU.h230 #define REG_MBX_BASE (0x0400) macro
294 #define VPU_REG_VERSION ( REG_MBX_BASE+(0x0055<<1))
295 #define VPU_REG_HI_MBOX0_L ( REG_MBX_BASE+(0x005b<<1))
296 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+( 0x005c<<1))
297 #define VPU_REG_HI_MBOX1_L ( REG_MBX_BASE+(0x005d<<1))
298 #define VPU_REG_HI_MBOX1_H ( REG_MBX_BASE+(0x005e<<1))
299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1))
302 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+( 0x0067<<1))
308 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
312 #define VPU_REG_HI_MBOX_RDY ( REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/vpu_ex/
H A DregVPU_EX.h230 #define REG_MBX_BASE (0x0400UL) macro
295 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
297 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
298 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
299 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
300 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
306 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
313 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
318 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/vpu_v3/
H A DregVPU_EX.h230 #define REG_MBX_BASE (0x0400) macro
296 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
298 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
299 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
300 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
301 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
303 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
307 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
314 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
319 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1))
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/vpu_ex/
H A DregVPU_EX.h230 #define REG_MBX_BASE (0x0400) macro
296 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1))
298 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1))
299 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1))
300 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1))
301 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1))
303 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1))
307 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1))
314 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1))
319 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1))
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