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Searched refs:REG_ISP_SPI_MODE (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/flash/hal/mooney/flash/serial/
H A DhalSERFLASH.c1384 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1388 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2556 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4255 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4258 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4261 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4262 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4265 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4268 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_QUAD_ENABLE, SFSH_CHIP_QUAD_MASK); in HAL_SERFLASH_SelectReadMode()
4523 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
[all …]
H A DregSERFLASH.h218 #define REG_ISP_SPI_MODE 0x72 macro
/utopia/UTPA2-700.0.x/modules/flash/hal/M7621/flash/serial/
H A DhalSERFLASH.c1421 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1425 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2593 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4292 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4295 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4298 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4299 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4302 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4305 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_QUAD_ENABLE, SFSH_CHIP_QUAD_MASK); in HAL_SERFLASH_SelectReadMode()
4560 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
[all …]
H A DregSERFLASH.h218 #define REG_ISP_SPI_MODE 0x72 macro
/utopia/UTPA2-700.0.x/modules/flash/hal/mainz/flash/serial/
H A DhalSERFLASH.c1392 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1396 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2566 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4265 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4268 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4271 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4272 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4275 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4278 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_QUAD_ENABLE, SFSH_CHIP_QUAD_MASK); in HAL_SERFLASH_SelectReadMode()
4533 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
[all …]
H A DregSERFLASH.h219 #define REG_ISP_SPI_MODE 0x72 macro
/utopia/UTPA2-700.0.x/modules/flash/hal/maserati/flash/serial/
H A DhalSERFLASH.c1421 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1425 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2593 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4292 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4295 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4298 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4299 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4302 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4305 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_QUAD_ENABLE, SFSH_CHIP_QUAD_MASK); in HAL_SERFLASH_SelectReadMode()
4560 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
[all …]
H A DregSERFLASH.h218 #define REG_ISP_SPI_MODE 0x72 macro
/utopia/UTPA2-700.0.x/modules/flash/hal/M7821/flash/serial/
H A DhalSERFLASH.c1421 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1425 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2593 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4292 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4295 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4298 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4299 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4302 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4305 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_QUAD_ENABLE, SFSH_CHIP_QUAD_MASK); in HAL_SERFLASH_SelectReadMode()
4560 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
[all …]
H A DregSERFLASH.h218 #define REG_ISP_SPI_MODE 0x72 macro
/utopia/UTPA2-700.0.x/modules/flash/hal/messi/flash/serial/
H A DhalSERFLASH.c1392 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1396 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2566 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4265 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4268 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4271 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4272 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4275 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4278 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_QUAD_ENABLE, SFSH_CHIP_QUAD_MASK); in HAL_SERFLASH_SelectReadMode()
4533 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
[all …]
H A DregSERFLASH.h219 #define REG_ISP_SPI_MODE 0x72 macro
/utopia/UTPA2-700.0.x/modules/flash/hal/maxim/flash/serial/
H A DhalSERFLASH.c1421 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1425 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2593 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4292 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4295 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4298 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4299 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4302 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4305 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_QUAD_ENABLE, SFSH_CHIP_QUAD_MASK); in HAL_SERFLASH_SelectReadMode()
4560 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
[all …]
H A DregSERFLASH.h218 #define REG_ISP_SPI_MODE 0x72 macro
/utopia/UTPA2-700.0.x/modules/flash/hal/macan/flash/serial/
H A DhalSERFLASH.c1384 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1388 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2556 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4255 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4258 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4261 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4262 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4265 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4268 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_QUAD_ENABLE, SFSH_CHIP_QUAD_MASK); in HAL_SERFLASH_SelectReadMode()
4523 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
[all …]
H A DregSERFLASH.h218 #define REG_ISP_SPI_MODE 0x72 macro
/utopia/UTPA2-700.0.x/modules/flash/hal/manhattan/flash/serial/
H A DhalSERFLASH.c1422 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1426 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2594 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4293 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4296 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4299 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4300 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_SelectReadMode()
4303 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_DADD_ENABLE, SFSH_CHIP_2XREAD_MASK); in HAL_SERFLASH_SelectReadMode()
4306 QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_QUAD_ENABLE, SFSH_CHIP_QUAD_MASK); in HAL_SERFLASH_SelectReadMode()
4561 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
[all …]
H A DregSERFLASH.h218 #define REG_ISP_SPI_MODE 0x72 macro
/utopia/UTPA2-700.0.x/modules/flash/hal/maldives/flash/serial/
H A DhalSERFLASH.c1516 ISP_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1520 ISP_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2332 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_FAST_ENABLE,SFSH_CHIP_FAST_MASK); in HAL_SERFLASH_DetectType()
2759 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4659 u8Mode = (HAL_Read2Byte(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
4660 HAL_Write2Byte(REG_ISP_SPI_MODE, 0x0000); in HAL_FSP_Entry()
4665 HAL_Write2Byte(REG_ISP_SPI_MODE, u8Mode); in HAL_FSP_Exit()
H A DregSERFLASH.h225 #define REG_ISP_SPI_MODE 0x72 macro
/utopia/UTPA2-700.0.x/modules/flash/hal/kano/flash/serial/
H A DhalSERFLASH.c1235 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1239 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2467 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4227 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
4228 FSP_WRITE(REG_ISP_SPI_MODE, 0x0000); in HAL_FSP_Entry()
4233 FSP_WRITE(REG_ISP_SPI_MODE, u8Mode); in HAL_FSP_Exit()
/utopia/UTPA2-700.0.x/modules/flash/hal/k6/flash/serial/
H A DhalSERFLASH.c1235 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1239 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2467 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4227 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
4228 FSP_WRITE(REG_ISP_SPI_MODE, 0x0000); in HAL_FSP_Entry()
4233 FSP_WRITE(REG_ISP_SPI_MODE, u8Mode); in HAL_FSP_Exit()
/utopia/UTPA2-700.0.x/modules/flash/hal/curry/flash/serial/
H A DhalSERFLASH.c1235 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1239 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2481 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4241 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
4242 FSP_WRITE(REG_ISP_SPI_MODE, 0x0000); in HAL_FSP_Entry()
4247 FSP_WRITE(REG_ISP_SPI_MODE, u8Mode); in HAL_FSP_Exit()
/utopia/UTPA2-700.0.x/modules/flash/hal/k6lite/flash/serial/
H A DhalSERFLASH.c1258 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DADD_ENABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
1262 QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); in _HAL_ISP_2XMode()
2486 b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; in HAL_SERFLASH_Write()
4247 u8Mode = (FSP_READ(REG_ISP_SPI_MODE) & 0x000F); in HAL_FSP_Entry()
4248 FSP_WRITE(REG_ISP_SPI_MODE, 0x0000); in HAL_FSP_Entry()
4253 FSP_WRITE(REG_ISP_SPI_MODE, u8Mode); in HAL_FSP_Exit()
H A DregSERFLASH.h227 #define REG_ISP_SPI_MODE 0x72 macro

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