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Searched refs:REG_HDCP2_BASE (Results 1 – 25 of 46) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP2_09_L (REG_HDCP2_BASE + 0x12)
142 #define REG_HDCP2_09_H (REG_HDCP2_BASE + 0x13)
143 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
144 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
145 #define REG_HDCP2_1B_L (REG_HDCP2_BASE + 0x36)
146 #define REG_HDCP2_1B_H (REG_HDCP2_BASE + 0x37)
147 #define REG_HDCP2_1C_L (REG_HDCP2_BASE + 0x38)
148 #define REG_HDCP2_1C_H (REG_HDCP2_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP2_09_L (REG_HDCP2_BASE + 0x12)
142 #define REG_HDCP2_09_H (REG_HDCP2_BASE + 0x13)
143 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
144 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
145 #define REG_HDCP2_1B_L (REG_HDCP2_BASE + 0x36)
146 #define REG_HDCP2_1B_H (REG_HDCP2_BASE + 0x37)
147 #define REG_HDCP2_1C_L (REG_HDCP2_BASE + 0x38)
148 #define REG_HDCP2_1C_H (REG_HDCP2_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0 // HDCP started from 0xC0 macro
164 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
165 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
166 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0 // HDCP started from 0xC0 macro
164 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
165 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
166 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/cec/include/
H A Dcec_hwreg.h132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 macro
167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02)
168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A)
169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdcp.h167 #define REG_HDCP2_1C_L (REG_HDCP2_BASE + 0x38)
168 #define REG_HDCP2_1C_H (REG_HDCP2_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdcp.h167 #define REG_HDCP2_1C_L (REG_HDCP2_BASE + 0x38)
168 #define REG_HDCP2_1C_H (REG_HDCP2_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdcp.h167 #define REG_HDCP2_1C_L (REG_HDCP2_BASE + 0x38)
168 #define REG_HDCP2_1C_H (REG_HDCP2_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdcp.h167 #define REG_HDCP2_1C_L (REG_HDCP2_BASE + 0x38)
168 #define REG_HDCP2_1C_H (REG_HDCP2_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdcp.h167 #define REG_HDCP2_1C_L (REG_HDCP2_BASE + 0x38)
168 #define REG_HDCP2_1C_H (REG_HDCP2_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdcp.h167 #define REG_HDCP2_1C_L (REG_HDCP2_BASE + 0x38)
168 #define REG_HDCP2_1C_H (REG_HDCP2_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdcp.h167 #define REG_HDCP2_1C_L (REG_HDCP2_BASE + 0x38)
168 #define REG_HDCP2_1C_H (REG_HDCP2_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdcp.h167 #define REG_HDCP2_1C_L (REG_HDCP2_BASE + 0x38)
168 #define REG_HDCP2_1C_H (REG_HDCP2_BASE + 0x39)

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