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Searched refs:REG_FSC_BK23_79 (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c84 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x00, 0x0f); // gb_in_size_F1 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
85 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x10, 0x10); // gb_in_en_F1 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
552 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x00, 0x0f); // gb_in_size_F1 in MFC_3D_2D_4K2K_2D_FHD_YUV()
553 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x10, 0x10); // gb_in_en_F1 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1020 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x00, 0x0f); // gb_in_size_F1 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1021 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x10, 0x10); // gb_in_en_F1 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1488 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x00, 0x0f); // gb_in_size_F1 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1489 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x10, 0x10); // gb_in_en_F1 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A Dhwreg_frc_map.h11162 #define REG_FSC_BK23_79 (REG_FSC_BANK_BASE+0x2379) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c84 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x00, 0x0f); // gb_in_size_F1 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
85 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x10, 0x10); // gb_in_en_F1 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
552 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x00, 0x0f); // gb_in_size_F1 in MFC_3D_2D_4K2K_2D_FHD_YUV()
553 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x10, 0x10); // gb_in_en_F1 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1020 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x00, 0x0f); // gb_in_size_F1 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1021 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x10, 0x10); // gb_in_en_F1 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1488 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x00, 0x0f); // gb_in_size_F1 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1489 MDrv_WriteByteMask( REG_FSC_BK23_79, 0x10, 0x10); // gb_in_en_F1 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A Dhwreg_frc_map.h11163 #define REG_FSC_BK23_79 (REG_FSC_BANK_BASE+0x2379) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_frc_map.h12255 #define REG_FSC_BK23_79 (REG_FSC_BANK_BASE+0x2379) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_frc_map.h12255 #define REG_FSC_BK23_79 (REG_FSC_BANK_BASE+0x2379) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h12771 #define REG_FSC_BK23_79 (REG_FSC_BANK_BASE+0x2379) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h12770 #define REG_FSC_BK23_79 (REG_FSC_BANK_BASE+0x2379) macro