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Searched refs:REG_FRC_BK3E_82 (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c409 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
830 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
1251 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1672 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2093 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2514 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c409 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
830 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c438 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
888 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c438 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
888 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c438 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
888 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c409 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
830 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
1251 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1672 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2093 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2514 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c409 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
830 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c438 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
888 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c438 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
888 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c438 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
888 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
676 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
1020 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1364 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
676 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
676 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
1020 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1364 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
676 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c456 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
924 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
1392 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1860 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c456 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
924 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
1392 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1860 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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