REG_FRC_BK33A_50 (reference) in projects: utopia

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched refs:REG_FRC_BK33A_50 (Results 1 – 25 of 54) sorted by relevance

12 3

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A D	Maserati_2D_4K2K.c	102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 523 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_YUV() 524 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_YUV() 525 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_YUV() 944 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 945 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 946 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1365 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_YUV() [all …]
H A D	Maserati_2D_FHD.c	102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 523 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_FHD_2D_FHD_YUV() 524 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_FHD_2D_FHD_YUV() 525 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_FHD_2D_FHD_YUV()
H A D	Maserati_2D_480.c	102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_480_2D_480_RGB_BYPASS() 103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_480_2D_480_RGB_BYPASS() 104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_480_2D_480_RGB_BYPASS() 552 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_480_2D_480_YUV() 553 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_480_2D_480_YUV() 554 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_480_2D_480_YUV()
H A D	Maserati_2D_576.c	102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_576_2D_576_RGB_BYPASS() 103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_576_2D_576_RGB_BYPASS() 104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_576_2D_576_RGB_BYPASS() 552 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_576_2D_576_YUV() 553 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_576_2D_576_YUV() 554 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_576_2D_576_YUV()
H A D	Maserati_2D_720.c	102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_720_2D_720_RGB_BYPASS() 103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_720_2D_720_RGB_BYPASS() 104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_720_2D_720_RGB_BYPASS() 552 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_720_2D_720_YUV() 553 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_720_2D_720_YUV() 554 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A D	Maserati_2D_4K2K.c	102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 523 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_YUV() 524 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_YUV() 525 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_YUV() 944 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 945 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 946 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1365 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_YUV() [all …]
H A D	Maserati_2D_FHD.c	102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 523 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_FHD_2D_FHD_YUV() 524 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_FHD_2D_FHD_YUV() 525 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_FHD_2D_FHD_YUV()
H A D	Maserati_2D_720.c	102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_720_2D_720_RGB_BYPASS() 103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_720_2D_720_RGB_BYPASS() 104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_720_2D_720_RGB_BYPASS() 552 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_720_2D_720_YUV() 553 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_720_2D_720_YUV() 554 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_720_2D_720_YUV()
H A D	Maserati_2D_480.c	102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_480_2D_480_RGB_BYPASS() 103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_480_2D_480_RGB_BYPASS() 104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_480_2D_480_RGB_BYPASS() 552 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_480_2D_480_YUV() 553 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_480_2D_480_YUV() 554 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_480_2D_480_YUV()
H A D	Maserati_2D_576.c	102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_576_2D_576_RGB_BYPASS() 103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_576_2D_576_RGB_BYPASS() 104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_576_2D_576_RGB_BYPASS() 552 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_576_2D_576_YUV() 553 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_576_2D_576_YUV() 554 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A D	Maxim_2D_4K2K.c	47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 391 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_YUV() 392 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_YUV() 393 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_YUV() 735 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 736 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 737 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1079 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_YUV() [all …]
H A D	Maxim_2D_FHD.c	47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 391 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_FHD_2D_FHD_YUV() 392 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_FHD_2D_FHD_YUV() 393 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_FHD_2D_FHD_YUV()
H A D	Maxim_ACT_4K0_5K.c	`47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_ACT_4K1K.c	`47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K2K_120.c	`47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A D	Maxim_2D_4K2K.c	47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 391 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_YUV() 392 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_YUV() 393 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_YUV() 735 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 736 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 737 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1079 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_YUV() [all …]
H A D	Maxim_2D_FHD.c	47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 391 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_FHD_2D_FHD_YUV() 392 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_FHD_2D_FHD_YUV() 393 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_FHD_2D_FHD_YUV()
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_PAS_4K2K_120.c	`47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_120.c	`47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB() 48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB() 49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A D	Manhattan_2D_4K2K.c	113 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 114 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 115 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 581 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_YUV() 582 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_YUV() 583 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_YUV() 1049 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1050 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1051 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1517 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_YUV() [all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A D	Manhattan_2D_4K2K.c	113 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 114 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 115 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 581 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_FHD_YUV() 582 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_FHD_YUV() 583 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_FHD_YUV() 1049 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1050 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1051 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1517 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass in MFC_3D_2D_4K2K_2D_4K2K_YUV() [all …]

12 3