Home
last modified time | relevance | path

Searched refs:REG_FRC_BK33A_46 (Results 1 – 25 of 54) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
534 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_YUV()
955 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1376 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1797 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2218 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
534 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_480_2D_480_RGB_BYPASS()
563 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_576_2D_576_RGB_BYPASS()
563 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_720_2D_720_RGB_BYPASS()
563 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
534 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_YUV()
955 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1376 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1797 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2218 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
534 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_720_2D_720_RGB_BYPASS()
563 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_480_2D_480_RGB_BYPASS()
563 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_576_2D_576_RGB_BYPASS()
563 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
402 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_YUV()
746 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1090 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
402 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
402 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_YUV()
746 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1090 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
402 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c124 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
592 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_YUV()
1060 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1528 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c124 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
592 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_FHD_YUV()
1060 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1528 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end in MFC_3D_2D_4K2K_2D_4K2K_YUV()

123