REG_FRC_BK2E_E0 (reference) in projects: utopia

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Searched refs:REG_FRC_BK2E_E0 (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A D	Maserati_2D_4K2K.c	368 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 369 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 377 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 789 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 790 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 798 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 1210 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1211 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1219 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1631 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() [all …]
H A D	Maserati_2D_FHD.c	368 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 369 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 377 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 789 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_FHD_2D_FHD_YUV() 790 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_FHD_2D_FHD_YUV() 798 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_FHD_2D_FHD_YUV()
H A D	Maserati_2D_480.c	366 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 367 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 375 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 816 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_480_2D_480_YUV() 817 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_480_2D_480_YUV() 825 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_480_2D_480_YUV()
H A D	Maserati_2D_576.c	366 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 367 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 375 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 816 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_576_2D_576_YUV() 817 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_576_2D_576_YUV() 825 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_576_2D_576_YUV()
H A D	Maserati_2D_720.c	366 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 367 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 375 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 816 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_720_2D_720_YUV() 817 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_720_2D_720_YUV() 825 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A D	Maserati_2D_4K2K.c	368 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 369 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 377 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 789 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 790 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 798 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 1210 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1211 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1219 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1631 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() [all …]
H A D	Maserati_2D_FHD.c	368 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 369 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 377 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 789 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_FHD_2D_FHD_YUV() 790 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_FHD_2D_FHD_YUV() 798 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_FHD_2D_FHD_YUV()
H A D	Maserati_2D_720.c	366 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 367 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 375 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 816 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_720_2D_720_YUV() 817 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_720_2D_720_YUV() 825 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_720_2D_720_YUV()
H A D	Maserati_2D_480.c	366 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 367 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 375 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 816 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_480_2D_480_YUV() 817 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_480_2D_480_YUV() 825 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_480_2D_480_YUV()
H A D	Maserati_2D_576.c	366 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 367 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 375 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 816 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_576_2D_576_YUV() 817 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_576_2D_576_YUV() 825 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A D	Maxim_2D_4K2K.c	309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 653 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 654 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 662 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 997 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 998 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1006 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1341 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() [all …]
H A D	Maxim_2D_FHD.c	309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 653 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_FHD_2D_FHD_YUV() 654 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_FHD_2D_FHD_YUV() 662 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_FHD_2D_FHD_YUV()
H A D	Maxim_ACT_4K0_5K.c	`309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x04, 0x04); // reg_snr_la_en in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x10, 0x10); // reg_lbi_vsu2x_en in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x04, 0x04); // reg_snr_la_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_ACT_4K1K.c	`309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x04, 0x04); // reg_snr_la_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x10, 0x10); // reg_lbi_vsu2x_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K2K_120.c	`309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x04, 0x04); // reg_snr_la_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x10, 0x10); // reg_lbi_vsu2x_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A D	Maxim_2D_4K2K.c	309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 653 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 654 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 662 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 997 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 998 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1006 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1341 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() [all …]
H A D	Maxim_2D_FHD.c	309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 653 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_FHD_2D_FHD_YUV() 654 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_2D_FHD_2D_FHD_YUV() 662 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_FHD_2D_FHD_YUV()
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_PAS_4K2K_120.c	`309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x04, 0x04); // reg_snr_la_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x04, 0x04); // reg_snr_la_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_120.c	`309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB() 310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x04, 0x04); // reg_snr_la_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB() 318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A D	Manhattan_2D_4K2K.c	373 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 379 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 841 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 847 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 1309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1315 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1777 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1783 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A D	Manhattan_2D_4K2K.c	373 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 379 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 841 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 847 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 1309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1315 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1777 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1783 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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