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Searched refs:REG_FRC_BK233_46 (Results 1 – 25 of 50) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
739 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_FHD_YUV()
1160 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1581 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2002 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2423 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
739 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_480_2D_480_RGB_BYPASS()
768 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_576_2D_576_RGB_BYPASS()
768 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_720_2D_720_RGB_BYPASS()
768 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
739 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_FHD_YUV()
1160 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1581 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2002 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2423 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
739 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_720_2D_720_RGB_BYPASS()
768 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_480_2D_480_RGB_BYPASS()
768 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_576_2D_576_RGB_BYPASS()
768 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
605 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_FHD_YUV()
949 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1293 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
605 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_60.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
605 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_FHD_YUV()
949 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1293 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
605 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x80, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()

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