Home
last modified time | relevance | path

Searched refs:REG_FRC_BK233_3F (Results 1 – 25 of 50) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
736 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_FHD_YUV()
1157 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1578 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1999 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2420 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
736 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_480_2D_480_RGB_BYPASS()
765 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_576_2D_576_RGB_BYPASS()
765 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_720_2D_720_RGB_BYPASS()
765 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
736 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_FHD_YUV()
1157 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1578 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1999 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2420 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
736 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_720_2D_720_RGB_BYPASS()
765 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_480_2D_480_RGB_BYPASS()
765 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_576_2D_576_RGB_BYPASS()
765 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
602 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_FHD_YUV()
946 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1290 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
602 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_60.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
602 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_FHD_YUV()
946 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1290 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
602 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x07, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()

12