REG_FRC_BK13C_CD (reference) in projects: utopia

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Searched refs:REG_FRC_BK13C_CD (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A D	Maserati_2D_4K2K.c	186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 607 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 630 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1028 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1051 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1449 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1472 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1870 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 1893 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 607 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 630 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_480.c	`186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_RGB_BYPASS() 209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_RGB_BYPASS() 636 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_YUV() 659 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_RGB_BYPASS() 209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_RGB_BYPASS() 636 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_YUV() 659 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_YUV()`
H A D	Maserati_2D_720.c	`186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_RGB_BYPASS() 209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_RGB_BYPASS() 636 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_YUV() 659 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A D	Maserati_2D_4K2K.c	186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 607 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 630 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1028 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1051 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1449 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1472 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1870 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 1893 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 607 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 630 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_720.c	`186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_RGB_BYPASS() 209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_RGB_BYPASS() 636 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_YUV() 659 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_YUV()`
H A D	Maserati_2D_480.c	`186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_RGB_BYPASS() 209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_RGB_BYPASS() 636 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_YUV() 659 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_RGB_BYPASS() 209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_RGB_BYPASS() 636 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_YUV() 659 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A D	Maxim_2D_4K2K.c	129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 473 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 496 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 817 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 840 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1161 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1184 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 473 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 496 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_ACT_4K0_5K.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x02, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_ACT_4K1K.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K2K_120.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A D	Maxim_2D_4K2K.c	129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 473 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 496 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 817 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 840 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1161 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1184 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 473 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 496 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x02, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_PAS_4K2K_120.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_120.c	`129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB() 152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A D	Manhattan_2D_4K2K.c	197 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 220 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 665 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 688 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1133 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1156 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1601 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1624 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A D	Manhattan_2D_4K2K.c	197 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 220 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 665 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 688 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1133 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1156 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1601 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1624 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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