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Searched refs:REG_FRC_BK13C_75 (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c406 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
874 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1342 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1810 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A Dhwreg_frc_map.h8830 #define REG_FRC_BK13C_75 (REG_FRC_BANK_BASE+0x13C75) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c406 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
874 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1342 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1810 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A Dhwreg_frc_map.h8830 #define REG_FRC_BK13C_75 (REG_FRC_BANK_BASE+0x13C75) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_720.c400 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_720_2D_720_RGB_BYPASS()
850 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c400 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_480_2D_480_RGB_BYPASS()
850 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c400 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_576_2D_576_RGB_BYPASS()
850 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_576_2D_576_YUV()
H A Dhwreg_frc_map.h9148 #define REG_FRC_BK13C_75 (REG_FRC_BANK_BASE+0x13C75) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_480.c400 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_480_2D_480_RGB_BYPASS()
850 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c400 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_576_2D_576_RGB_BYPASS()
850 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c400 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_720_2D_720_RGB_BYPASS()
850 MDrv_WriteByteMask( REG_FRC_BK13C_75 , 0x40, 0xff); // reg_hsu_coef05 in MFC_3D_2D_720_2D_720_YUV()
H A Dhwreg_frc_map.h9148 #define REG_FRC_BK13C_75 (REG_FRC_BANK_BASE+0x13C75) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h9148 #define REG_FRC_BK13C_75 (REG_FRC_BANK_BASE+0x13C75) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h9148 #define REG_FRC_BK13C_75 (REG_FRC_BANK_BASE+0x13C75) macro