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Searched refs:REG_FRC_BK13B_D0 (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c389 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
390 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
391 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
857 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_FHD_YUV()
858 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_FHD_YUV()
859 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_FHD_YUV()
1325 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1326 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1327 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1793 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_4K2K_YUV()
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H A Dhwreg_frc_map.h8663 #define REG_FRC_BK13B_D0 (REG_FRC_BANK_BASE+0x13BD0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c389 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
390 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
391 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
857 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_FHD_YUV()
858 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_FHD_YUV()
859 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_FHD_YUV()
1325 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1326 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1327 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1793 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_4K2K_YUV()
[all …]
H A Dhwreg_frc_map.h8663 #define REG_FRC_BK13B_D0 (REG_FRC_BANK_BASE+0x13BD0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_720.c385 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_720_2D_720_RGB_BYPASS()
386 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_720_2D_720_RGB_BYPASS()
387 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_720_2D_720_RGB_BYPASS()
835 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_720_2D_720_YUV()
836 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_720_2D_720_YUV()
837 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c385 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_480_2D_480_RGB_BYPASS()
386 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_480_2D_480_RGB_BYPASS()
387 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_480_2D_480_RGB_BYPASS()
835 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_480_2D_480_YUV()
836 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_480_2D_480_YUV()
837 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c385 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_576_2D_576_RGB_BYPASS()
386 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_576_2D_576_RGB_BYPASS()
387 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_576_2D_576_RGB_BYPASS()
835 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_576_2D_576_YUV()
836 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_576_2D_576_YUV()
837 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_576_2D_576_YUV()
H A Dhwreg_frc_map.h8981 #define REG_FRC_BK13B_D0 (REG_FRC_BANK_BASE+0x13BD0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_480.c385 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_480_2D_480_RGB_BYPASS()
386 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_480_2D_480_RGB_BYPASS()
387 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_480_2D_480_RGB_BYPASS()
835 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_480_2D_480_YUV()
836 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_480_2D_480_YUV()
837 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c385 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_576_2D_576_RGB_BYPASS()
386 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_576_2D_576_RGB_BYPASS()
387 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_576_2D_576_RGB_BYPASS()
835 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_576_2D_576_YUV()
836 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_576_2D_576_YUV()
837 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c385 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_720_2D_720_RGB_BYPASS()
386 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_720_2D_720_RGB_BYPASS()
387 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_720_2D_720_RGB_BYPASS()
835 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x01); // reg_render_control in MFC_3D_2D_720_2D_720_YUV()
836 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_720_2D_720_YUV()
837 MDrv_WriteByteMask( REG_FRC_BK13B_D0 , 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_720_2D_720_YUV()
H A Dhwreg_frc_map.h8981 #define REG_FRC_BK13B_D0 (REG_FRC_BANK_BASE+0x13BD0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h8981 #define REG_FRC_BK13B_D0 (REG_FRC_BANK_BASE+0x13BD0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h8981 #define REG_FRC_BK13B_D0 (REG_FRC_BANK_BASE+0x13BD0) macro