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Searched refs:REG_FRC_BK13B_CD (Results 1 – 25 of 54) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
606 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV()
628 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV()
1027 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1049 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1448 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1470 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1869 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
1891 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
[all …]
H A DMaserati_2D_FHD.c185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
606 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV()
628 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_RGB_BYPASS()
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_RGB_BYPASS()
635 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_YUV()
657 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_RGB_BYPASS()
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_RGB_BYPASS()
635 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_YUV()
657 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_RGB_BYPASS()
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_RGB_BYPASS()
635 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_YUV()
657 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
606 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV()
628 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV()
1027 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1049 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1448 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1470 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1869 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
1891 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
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H A DMaserati_2D_FHD.c185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
606 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV()
628 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_RGB_BYPASS()
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_RGB_BYPASS()
635 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_YUV()
657 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_RGB_BYPASS()
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_RGB_BYPASS()
635 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_YUV()
657 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_RGB_BYPASS()
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_RGB_BYPASS()
635 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_YUV()
657 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
472 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV()
494 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV()
816 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
838 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1160 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1182 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
472 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV()
494 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x02, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
472 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV()
494 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV()
816 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
838 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1160 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1182 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
472 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV()
494 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x02, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c196 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
218 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
664 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV()
686 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV()
1132 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1154 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1600 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1622 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c196 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
218 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
664 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV()
686 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV()
1132 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1154 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1600 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1622 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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