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Searched refs:REG_FRC_BK13B_C6 (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c387 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
388 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
855 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
856 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
1323 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1324 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1791 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1792 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A Dhwreg_frc_map.h8653 #define REG_FRC_BK13B_C6 (REG_FRC_BANK_BASE+0x13BC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c387 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
388 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
855 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
856 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
1323 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1324 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1791 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1792 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A Dhwreg_frc_map.h8653 #define REG_FRC_BK13B_C6 (REG_FRC_BANK_BASE+0x13BC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_720.c383 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
384 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
833 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_720_2D_720_YUV()
834 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c383 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
384 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
833 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_480_2D_480_YUV()
834 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c383 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
384 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
833 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_576_2D_576_YUV()
834 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_576_2D_576_YUV()
H A Dhwreg_frc_map.h8971 #define REG_FRC_BK13B_C6 (REG_FRC_BANK_BASE+0x13BC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_480.c383 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
384 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
833 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_480_2D_480_YUV()
834 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c383 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
384 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
833 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_576_2D_576_YUV()
834 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c383 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
384 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
833 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x01, 0x01); // reg_srclb_en in MFC_3D_2D_720_2D_720_YUV()
834 MDrv_WriteByteMask( REG_FRC_BK13B_C6 , 0x02, 0x02); // reg_depthlb_en in MFC_3D_2D_720_2D_720_YUV()
H A Dhwreg_frc_map.h8971 #define REG_FRC_BK13B_C6 (REG_FRC_BANK_BASE+0x13BC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h8971 #define REG_FRC_BK13B_C6 (REG_FRC_BANK_BASE+0x13BC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h8971 #define REG_FRC_BK13B_C6 (REG_FRC_BANK_BASE+0x13BC6) macro