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Searched refs:REG_FRC_BK13B_C5 (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c385 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
386 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
853 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_FHD_YUV()
854 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_FHD_YUV()
1321 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1322 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1789 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1790 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A Dhwreg_frc_map.h8652 #define REG_FRC_BK13B_C5 (REG_FRC_BANK_BASE+0x13BC5) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c385 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
386 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
853 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_FHD_YUV()
854 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_FHD_YUV()
1321 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1322 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1789 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1790 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A Dhwreg_frc_map.h8652 #define REG_FRC_BK13B_C5 (REG_FRC_BANK_BASE+0x13BC5) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_720.c381 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_720_2D_720_RGB_BYPASS()
382 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_720_2D_720_RGB_BYPASS()
831 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_720_2D_720_YUV()
832 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c381 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_480_2D_480_RGB_BYPASS()
382 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_480_2D_480_RGB_BYPASS()
831 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_480_2D_480_YUV()
832 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c381 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_576_2D_576_RGB_BYPASS()
382 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_576_2D_576_RGB_BYPASS()
831 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_576_2D_576_YUV()
832 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_576_2D_576_YUV()
H A Dhwreg_frc_map.h8970 #define REG_FRC_BK13B_C5 (REG_FRC_BANK_BASE+0x13BC5) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_480.c381 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_480_2D_480_RGB_BYPASS()
382 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_480_2D_480_RGB_BYPASS()
831 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_480_2D_480_YUV()
832 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c381 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_576_2D_576_RGB_BYPASS()
382 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_576_2D_576_RGB_BYPASS()
831 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_576_2D_576_YUV()
832 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c381 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_720_2D_720_RGB_BYPASS()
382 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_720_2D_720_RGB_BYPASS()
831 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x04, 0x1f); // reg_col_height in MFC_3D_2D_720_2D_720_YUV()
832 MDrv_WriteByteMask( REG_FRC_BK13B_C5 , 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_720_2D_720_YUV()
H A Dhwreg_frc_map.h8970 #define REG_FRC_BK13B_C5 (REG_FRC_BANK_BASE+0x13BC5) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h8970 #define REG_FRC_BK13B_C5 (REG_FRC_BANK_BASE+0x13BC5) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h8970 #define REG_FRC_BK13B_C5 (REG_FRC_BANK_BASE+0x13BC5) macro