REG_FRC_BK13A_30 (reference) in projects: utopia

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Searched refs:REG_FRC_BK13A_30 (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A D	Maserati_2D_4K2K.c	161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 582 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV() 1003 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1424 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1845 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 2266 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_2205_YUV()
H A D	Maserati_2D_FHD.c	`161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 582 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_480.c	`161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_480_2D_480_RGB_BYPASS() 611 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_576_2D_576_RGB_BYPASS() 611 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_576_2D_576_YUV()`
H A D	Maserati_2D_720.c	`161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_720_2D_720_RGB_BYPASS() 611 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_720_2D_720_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A D	Maserati_2D_4K2K.c	161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 582 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV() 1003 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1424 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1845 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 2266 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_2205_YUV()
H A D	Maserati_2D_FHD.c	`161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 582 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_720.c	`161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_720_2D_720_RGB_BYPASS() 611 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_720_2D_720_YUV()`
H A D	Maserati_2D_480.c	`161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_480_2D_480_RGB_BYPASS() 611 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_576_2D_576_RGB_BYPASS() 611 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_576_2D_576_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A D	Maxim_2D_4K2K.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 448 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV() 792 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1136 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()`
H A D	Maxim_2D_FHD.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 448 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_ACT_4K0_5K.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x1C, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_ACT_4K1K.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K2K_120.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A D	Maxim_2D_4K2K.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 448 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV() 792 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1136 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()`
H A D	Maxim_2D_FHD.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 448 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x1C, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_PAS_4K2K_120.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_120.c	`104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A D	Manhattan_2D_4K2K.c	`172 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 640 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV() 1108 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1576 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A D	Manhattan_2D_4K2K.c	`172 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 640 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV() 1108 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1576 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()`

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