REG_FRC_BK136_CD (reference) in projects: utopia

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Searched refs:REG_FRC_BK136_CD (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A D	Maserati_2D_4K2K.c	183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 604 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 624 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1025 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1045 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1446 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1466 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1867 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 1887 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 604 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 624 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_480.c	`183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_RGB_BYPASS() 203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_RGB_BYPASS() 633 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_YUV() 653 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_RGB_BYPASS() 203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_RGB_BYPASS() 633 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_YUV() 653 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_YUV()`
H A D	Maserati_2D_720.c	`183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_RGB_BYPASS() 203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_RGB_BYPASS() 633 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_YUV() 653 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A D	Maserati_2D_4K2K.c	183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 604 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 624 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1025 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1045 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1446 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1466 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1867 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 1887 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 604 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 624 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_720.c	`183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_RGB_BYPASS() 203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_RGB_BYPASS() 633 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_YUV() 653 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_YUV()`
H A D	Maserati_2D_480.c	`183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_RGB_BYPASS() 203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_RGB_BYPASS() 633 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_YUV() 653 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_RGB_BYPASS() 203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_RGB_BYPASS() 633 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_YUV() 653 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A D	Maxim_2D_4K2K.c	126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 470 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 490 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 814 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 834 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1158 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1178 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 470 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 490 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_ACT_4K0_5K.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x02, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_ACT_4K1K.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K2K_120.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A D	Maxim_2D_4K2K.c	126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 470 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 490 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 814 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 834 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1158 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1178 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 470 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 490 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x02, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_PAS_4K2K_120.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_120.c	`126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB() 146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A D	Manhattan_2D_4K2K.c	194 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 214 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 662 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 682 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1130 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1150 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1598 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1618 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A D	Manhattan_2D_4K2K.c	194 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 214 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 662 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 682 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1130 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1150 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1598 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1618 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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