REG_FRC_BK134_CD (reference) in projects: utopia

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Searched refs:REG_FRC_BK134_CD (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A D	Maserati_2D_4K2K.c	182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 603 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 622 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1024 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1043 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1445 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1464 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1866 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 1885 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 603 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 622 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_480.c	`182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_RGB_BYPASS() 201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_RGB_BYPASS() 632 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_YUV() 651 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_RGB_BYPASS() 201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_RGB_BYPASS() 632 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_YUV() 651 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_YUV()`
H A D	Maserati_2D_720.c	`182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_RGB_BYPASS() 201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_RGB_BYPASS() 632 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_YUV() 651 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A D	Maserati_2D_4K2K.c	182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 603 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 622 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1024 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1043 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1445 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1464 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1866 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 1885 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 603 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 622 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_720.c	`182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_RGB_BYPASS() 201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_RGB_BYPASS() 632 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_YUV() 651 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_YUV()`
H A D	Maserati_2D_480.c	`182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_RGB_BYPASS() 201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_RGB_BYPASS() 632 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_YUV() 651 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_RGB_BYPASS() 201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_RGB_BYPASS() 632 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_YUV() 651 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A D	Maxim_2D_4K2K.c	125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 469 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 488 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 813 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 832 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1157 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1176 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 469 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 488 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_ACT_4K0_5K.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x02, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_ACT_4K1K.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K2K_120.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A D	Maxim_2D_4K2K.c	125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 469 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 488 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 813 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 832 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1157 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1176 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 469 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 488 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x02, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_PAS_4K2K_120.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_120.c	`125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB() 144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A D	Manhattan_2D_4K2K.c	193 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 212 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 661 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 680 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1129 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1148 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1597 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1616 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A D	Manhattan_2D_4K2K.c	193 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 212 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 661 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 680 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1129 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1148 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1597 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1616 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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