REG_FRC_BK115_33 (reference) in projects: utopia

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Searched refs:REG_FRC_BK115_33 (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A D	Maserati_2D_4K2K.c	400 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 401 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 821 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 822 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 1242 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1243 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1663 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1664 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 2084 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 2085 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`400 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 401 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 821 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_FHD_2D_FHD_YUV() 822 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_480.c	`429 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 430 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 879 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_480_2D_480_YUV() 880 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`429 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 430 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 879 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_576_2D_576_YUV() 880 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_576_2D_576_YUV()`
H A D	Maserati_2D_720.c	`429 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 430 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 879 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_720_2D_720_YUV() 880 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_720_2D_720_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A D	Maserati_2D_4K2K.c	400 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 401 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 821 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 822 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 1242 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1243 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1663 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1664 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 2084 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 2085 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`400 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 401 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 821 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_FHD_2D_FHD_YUV() 822 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_720.c	`429 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 430 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 879 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_720_2D_720_YUV() 880 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_720_2D_720_YUV()`
H A D	Maserati_2D_480.c	`429 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 430 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 879 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_480_2D_480_YUV() 880 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`429 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 430 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 879 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_576_2D_576_YUV() 880 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_576_2D_576_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A D	Maxim_2D_4K2K.c	323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 667 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 668 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 1011 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1012 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1355 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1356 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 667 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_FHD_2D_FHD_YUV() 668 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_ACT_4K0_5K.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_ACT_4K1K.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K2K_120.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A D	Maxim_2D_4K2K.c	323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 667 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 668 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 1011 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1012 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1355 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1356 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 667 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_FHD_2D_FHD_YUV() 668 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_PAS_4K2K_120.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_120.c	`323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB() 324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A D	Manhattan_2D_4K2K.c	447 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 448 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 915 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 916 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 1383 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1384 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1851 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1852 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A D	Manhattan_2D_4K2K.c	447 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 448 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 915 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 916 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 1383 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1384 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1851 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1852 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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