Home
last modified time | relevance | path

Searched refs:REG_FRC_BK115_0C (Results 1 – 25 of 54) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c402 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
823 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1244 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1665 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2086 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2507 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c402 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
823 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c431 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_480_2D_480_RGB_BYPASS()
881 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c431 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_576_2D_576_RGB_BYPASS()
881 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c431 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_720_2D_720_RGB_BYPASS()
881 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c402 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
823 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1244 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1665 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2086 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2507 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c402 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
823 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c431 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_720_2D_720_RGB_BYPASS()
881 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c431 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_480_2D_480_RGB_BYPASS()
881 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c431 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_576_2D_576_RGB_BYPASS()
881 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
669 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1013 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1357 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
669 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
669 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1013 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1357 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
669 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x80, 0xff); // hsp_size_in0 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c449 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
917 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1385 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1853 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c449 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
917 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1385 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1853 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0 in MFC_3D_2D_4K2K_2D_4K2K_YUV()

123