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Searched refs:REG_DECR2_CTRL_BASE (Results 1 – 4 of 4) sorted by relevance

/utopia/UTPA2-700.0.x/modules/audio/hal/k6/audio/
H A DregAUDIO.h754 #define REG_DECR2_CTRL_BASE (REG_R2_0_CTRL_BASE) macro
768 #define REG_DECR2_CTRL (REG_DECR2_CTRL_BASE + 0x80)
771 #define REG_DECR2_ICMEM_BASE_LO (REG_DECR2_CTRL_BASE + 0x82)
772 #define REG_DECR2_ICMEM_BASE_HI (REG_DECR2_CTRL_BASE + 0x84)
775 #define REG_DECR2_ICMEM2_BASE_LO (REG_DECR2_CTRL_BASE + 0x8C)
776 #define REG_DECR2_ICMEM2_BASE_HI (REG_DECR2_CTRL_BASE + 0x8E)
778 #define REG_DECR2_DCMEM_BASE_LO (REG_DECR2_CTRL_BASE + 0x86)
779 #define REG_DECR2_DCMEM_BASE_HI (REG_DECR2_CTRL_BASE + 0x88)
781 #define REG_DECR2_DQMEM_BASE_LO (REG_DECR2_CTRL_BASE + 0x9A)
782 #define REG_DECR2_DQMEM_BASE_HI (REG_DECR2_CTRL_BASE + 0x9C)
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H A DhalAUR2.c286 …HAL_AUR2_WriteMaskByte((REG_DECR2_CTRL_BASE + 0x40), 0xFF, 0x10); //0x1129_40[5]¬O±±¨îD-side MIU… in HAL_DEC_R2_EnableR2()
516 tmp_H = HAL_AUR2_ReadReg(REG_DECR2_CTRL_BASE+0x12); in HAL_DEC_R2_SetCommInfo()
517 tmp_L = HAL_AUR2_ReadReg(REG_DECR2_CTRL_BASE+0x10); in HAL_DEC_R2_SetCommInfo()
627 tmp_H = HAL_AUR2_ReadReg(REG_DECR2_CTRL_BASE+0x12); in HAL_DEC_R2_GetCommInfo()
628 tmp_L = HAL_AUR2_ReadReg(REG_DECR2_CTRL_BASE+0x10); in HAL_DEC_R2_GetCommInfo()
/utopia/UTPA2-700.0.x/modules/audio/hal/k6lite/audio/
H A DregAUDIO.h758 #define REG_DECR2_CTRL_BASE (REG_R2_0_CTRL_BASE) macro
772 #define REG_DECR2_CTRL (REG_DECR2_CTRL_BASE + 0x80)
775 #define REG_DECR2_ICMEM_BASE_LO (REG_DECR2_CTRL_BASE + 0x82)
776 #define REG_DECR2_ICMEM_BASE_HI (REG_DECR2_CTRL_BASE + 0x84)
779 #define REG_DECR2_ICMEM2_BASE_LO (REG_DECR2_CTRL_BASE + 0x8C)
780 #define REG_DECR2_ICMEM2_BASE_HI (REG_DECR2_CTRL_BASE + 0x8E)
782 #define REG_DECR2_DCMEM_BASE_LO (REG_DECR2_CTRL_BASE + 0x86)
783 #define REG_DECR2_DCMEM_BASE_HI (REG_DECR2_CTRL_BASE + 0x88)
785 #define REG_DECR2_DQMEM_BASE_LO (REG_DECR2_CTRL_BASE + 0x9A)
786 #define REG_DECR2_DQMEM_BASE_HI (REG_DECR2_CTRL_BASE + 0x9C)
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H A DhalAUR2.c282 …HAL_AUR2_WriteMaskByte((REG_DECR2_CTRL_BASE + 0x40), 0xFF, 0x10); //0x1129_40[5]¬O±±¨îD-side MIU… in HAL_DEC_R2_EnableR2()
485 tmp_H = HAL_AUR2_ReadReg(REG_DECR2_CTRL_BASE+0x12); in HAL_DEC_R2_SetCommInfo()
486 tmp_L = HAL_AUR2_ReadReg(REG_DECR2_CTRL_BASE+0x10); in HAL_DEC_R2_SetCommInfo()
592 tmp_H = HAL_AUR2_ReadReg(REG_DECR2_CTRL_BASE+0x12); in HAL_DEC_R2_GetCommInfo()
593 tmp_L = HAL_AUR2_ReadReg(REG_DECR2_CTRL_BASE+0x10); in HAL_DEC_R2_GetCommInfo()