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Searched refs:REG_CLKGEN1_DC0_SYNTH (Results 1 – 1 of 1) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c277 #define REG_CLKGEN1_DC0_SYNTH 0x50UL macro
3422 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYNTH) &= ~REG_CLKGEN1_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
3425 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYNTH) &= ~REG_CLKGEN1_STC2_CW_EN; in HAL_TSP_SetSTCSynth()
3426 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYNTH) |= REG_CLKGEN1_STC2_CW_EN; in HAL_TSP_SetSTCSynth()
3427 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYNTH) &= ~REG_CLKGEN1_STC2_CW_EN; in HAL_TSP_SetSTCSynth()
3428 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYNTH) |= REG_CLKGEN1_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()
3431 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYNTH) &= ~REG_CLKGEN1_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
3434 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYNTH) &= ~REG_CLKGEN1_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
3435 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYNTH) |= REG_CLKGEN1_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
3436 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYNTH) &= ~REG_CLKGEN1_STC3_CW_EN; in HAL_TSP_SetSTCSynth()
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