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Searched refs:REG_CLKGEN0_TSN_CLK_TS2_SHIFT (Results 1 – 7 of 7) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c242 #define REG_CLKGEN0_TSN_CLK_TS2_SHIFT 0UL macro
2204 …SP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
2205 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
3244 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c256 #define REG_CLKGEN0_TSN_CLK_TS2_SHIFT 0UL macro
2226 …SP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
2227 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
3270 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c252 #define REG_CLKGEN0_TSN_CLK_TS2_SHIFT 8UL macro
2084 …SP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
2085 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
3208 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c258 #define REG_CLKGEN0_TSN_CLK_TS2_SHIFT 0UL macro
2279 …SP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
2280 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
3456 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c258 #define REG_CLKGEN0_TSN_CLK_TS2_SHIFT 0UL macro
2279 …SP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
2280 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
3439 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c261 #define REG_CLKGEN0_TSN_CLK_TS2_SHIFT 0UL macro
2350 …SP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
2351 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
3535 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN… in HAL_TSP_GetTSIF_Status()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c261 #define REG_CLKGEN0_TSN_CLK_TS2_SHIFT 0UL macro
2311 …SP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
2312 u32data |= (u32Clk<< REG_CLKGEN0_TSN_CLK_TS2_SHIFT); in HAL_TSP_SelPad_ClkInv()
3496 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN… in HAL_TSP_GetTSIF_Status()