Searched refs:REG_CLKGEN0_DC0_SYTNTH1 (Results 1 – 1 of 1) sorted by relevance
220 #define REG_CLKGEN0_DC0_SYTNTH1 0x70UL macro3413 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()3416 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()3417 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()3418 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()3419 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()