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Searched refs:REG_ADDR_DBC_Y_GAIN (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dlc/drv/dlc/
H A DMsDBC.c425 if (g_DbcParameters.bYGainCtrl && (REG_ADDR_DBC_Y_GAIN != REG_NULL)) in msAdjustYCGain()
426 msWriteByte(REG_ADDR_DBC_Y_GAIN, Y_Gain); in msAdjustYCGain()
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/mainz/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/maxim/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/maserati/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/mustang/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7621/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/mooney/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/kano/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/maldives/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/macan/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6lite/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/messi/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h158 #define REG_ADDR_DBC_Y_GAIN L_BK_DLC(0x14) //SC1A_28 (8bit) macro