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Searched refs:PQ_VSPRule_IP_NUM_Main (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A DManhattan_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 3 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A DManhattan_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
10 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/k6lite/pq/include/
H A Dk6lite_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 4 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A Dk6lite_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
11 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/curry/pq/include/
H A DKano_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 4 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A DCurry_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 4 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A DKano_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
11 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
H A DCurry_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
11 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/kano/pq/include/
H A DKano_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 4 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A DKano_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
11 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DMaserati_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 3 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A DMaserati_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
10 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/k6/pq/include/
H A Dk6_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 4 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A Dk6_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
11 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/include/
H A DMaxim_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 3 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A DMaxim_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
10 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/include/
H A DMooney_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 3 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A DMooney_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
10 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DMaxim_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 3 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A DMaxim_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
10 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DMaserati_Main_VSPRule.h2 #define PQ_VSPRule_IP_NUM_Main 3 macro
34 extern code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main];
35 extern code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main];
H A DMaserati_Main_VSPRule.c2 code U8 MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]=
10 code U8 MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/drv/pq/
H A DdrvPQ_cus.c3337 PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_Main; in _MDrv_PQ_Set_DisplayType_Main()