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Searched refs:PQ_GRULE_HDR_IP_NUM_Main (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/include/
H A DMooney_Main_GRule.h367 #define PQ_GRULE_HDR_IP_NUM_Main 6 macro
424 extern code U8 MST_GRule_HDR_IP_Index_Main[PQ_GRULE_HDR_IP_NUM_Main];
425 …code U8 MST_GRule_HDR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_HDR_NUM_Main][PQ_GRULE_HDR_IP_NUM_Main];
H A DMooney_Main_GRule.c107 code U8 MST_GRule_HDR_IP_Index_Main[PQ_GRULE_HDR_IP_NUM_Main]=
46204 code U8 MST_GRule_HDR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_HDR_NUM_Main][PQ_GRULE_HDR_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DMaserati_Main_GRule.h349 #define PQ_GRULE_HDR_IP_NUM_Main 2 macro
401 extern code U8 MST_GRule_HDR_IP_Index_Main[PQ_GRULE_HDR_IP_NUM_Main];
402 …code U8 MST_GRule_HDR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_HDR_NUM_Main][PQ_GRULE_HDR_IP_NUM_Main];
H A DMaserati_Main_GRule.c103 code U8 MST_GRule_HDR_IP_Index_Main[PQ_GRULE_HDR_IP_NUM_Main]=
58276 code U8 MST_GRule_HDR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_HDR_NUM_Main][PQ_GRULE_HDR_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/include/
H A DMaxim_Main_GRule.h347 #define PQ_GRULE_HDR_IP_NUM_Main 12 macro
399 extern code U8 MST_GRule_HDR_IP_Index_Main[PQ_GRULE_HDR_IP_NUM_Main];
400 …code U8 MST_GRule_HDR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_HDR_NUM_Main][PQ_GRULE_HDR_IP_NUM_Main];
H A DMaxim_Main_GRule.c103 code U8 MST_GRule_HDR_IP_Index_Main[PQ_GRULE_HDR_IP_NUM_Main]=
56886 code U8 MST_GRule_HDR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_HDR_NUM_Main][PQ_GRULE_HDR_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DMaxim_Main_GRule.h347 #define PQ_GRULE_HDR_IP_NUM_Main 12 macro
399 extern code U8 MST_GRule_HDR_IP_Index_Main[PQ_GRULE_HDR_IP_NUM_Main];
400 …code U8 MST_GRule_HDR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_HDR_NUM_Main][PQ_GRULE_HDR_IP_NUM_Main];
H A DMaxim_Main_GRule.c103 code U8 MST_GRule_HDR_IP_Index_Main[PQ_GRULE_HDR_IP_NUM_Main]=
56886 code U8 MST_GRule_HDR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_HDR_NUM_Main][PQ_GRULE_HDR_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DMaserati_Main_GRule.h349 #define PQ_GRULE_HDR_IP_NUM_Main 9 macro
401 extern code U8 MST_GRule_HDR_IP_Index_Main[PQ_GRULE_HDR_IP_NUM_Main];
402 …code U8 MST_GRule_HDR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_HDR_NUM_Main][PQ_GRULE_HDR_IP_NUM_Main];
H A DMaserati_Main_GRule.c103 code U8 MST_GRule_HDR_IP_Index_Main[PQ_GRULE_HDR_IP_NUM_Main]=
56883 code U8 MST_GRule_HDR_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_HDR_NUM_Main][PQ_GRULE_HDR_IP_NUM_Main]=
/utopia/UTPA2-700.0.x/modules/pq/drv/pq/
H A DdrvPQ_cus.c3438 PQTableInfo.u8PQ_GRule_IPNum[E_GRule_HDR_Main] = PQ_GRULE_HDR_IP_NUM_Main; in _MDrv_PQ_Set_DisplayType_Main()
H A DdrvPQ.c6639 for(i=0; i<PQ_GRULE_HDR_IP_NUM_Main; i++) in _MDrv_PQ_LoadHDRModeTable()