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Searched refs:PMSLEEP_REG_BASE (Results 1 – 25 of 34) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/bdma/hal/kano/bdma/
H A DhalBDMA.c992 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
993 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
1022 HAL_BDMA_Write2Byte(PMSLEEP_REG_BASE+0x54,0x829f); in HAL_BDMA_SetSPIOffsetForMCU()
1053 HAL_BDMA_Write2Byte(PMSLEEP_REG_BASE+0x54,0x829f); in HAL_BDMA_SetSPIOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/bdma/hal/k6/bdma/
H A DhalBDMA.c992 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
993 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
1022 HAL_BDMA_Write2Byte(PMSLEEP_REG_BASE+0x54,0x829f); in HAL_BDMA_SetSPIOffsetForMCU()
1053 HAL_BDMA_Write2Byte(PMSLEEP_REG_BASE+0x54,0x829f); in HAL_BDMA_SetSPIOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/bdma/hal/curry/bdma/
H A DhalBDMA.c992 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
993 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
1022 HAL_BDMA_Write2Byte(PMSLEEP_REG_BASE+0x54,0x829f); in HAL_BDMA_SetSPIOffsetForMCU()
1053 HAL_BDMA_Write2Byte(PMSLEEP_REG_BASE+0x54,0x829f); in HAL_BDMA_SetSPIOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/k6lite/pm/
H A DhalPM.c656 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
657 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
737 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
787 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetDRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/k6/pm/
H A DhalPM.c655 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
656 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
736 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
786 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetDRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/curry/pm/
H A DhalPM.c656 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
657 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
737 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
787 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetDRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/kano/pm/
H A DhalPM.c656 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
657 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
737 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
787 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetDRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/bdma/hal/k6lite/bdma/
H A DhalBDMA.c992 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
993 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
1037 HAL_BDMA_Write2Byte(PMSLEEP_REG_BASE+0x54,0x829f); in HAL_BDMA_SetSPIOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/maldives/pm/
H A DhalPM.c524 #define PMSLEEP_REG_BASE 0x0e00 //0x000e00 macro
525 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
616 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54,0x829f); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/mustang/pm/
H A DhalPM.c524 #define PMSLEEP_REG_BASE 0x0e00 //0x000e00 macro
525 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
616 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54,0x829f); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/mainz/pm/
H A DhalPM.c525 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
526 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
617 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/maserati/pm/
H A DhalPM.c523 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
524 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
615 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/manhattan/pm/
H A DhalPM.c523 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
524 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
615 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/M7621/pm/
H A DhalPM.c523 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
524 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
615 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/maxim/pm/
H A DhalPM.c523 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
524 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
615 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/mooney/pm/
H A DhalPM.c523 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
524 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
615 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/M7821/pm/
H A DhalPM.c523 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
524 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
615 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/macan/pm/
H A DhalPM.c525 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
526 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
617 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/pm/hal/messi/pm/
H A DhalPM.c525 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
526 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29UL*2)
617 HAL_PM_Write2Byte(PMSLEEP_REG_BASE+0x54UL,0x829fUL); in HAL_PM_SetSRAMOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/bdma/hal/maldives/bdma/
H A DhalBDMA.c862 #define PMSLEEP_REG_BASE 0x0e00 //0x000e00 macro
863 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
/utopia/UTPA2-700.0.x/modules/bdma/hal/mustang/bdma/
H A DhalBDMA.c864 #define PMSLEEP_REG_BASE 0x0e00 //0x000e00 macro
865 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
/utopia/UTPA2-700.0.x/modules/bdma/hal/mooney/bdma/
H A DhalBDMA.c981 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
982 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
/utopia/UTPA2-700.0.x/modules/bdma/hal/macan/bdma/
H A DhalBDMA.c981 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
982 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
/utopia/UTPA2-700.0.x/modules/bdma/hal/maserati/bdma/
H A DhalBDMA.c979 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
980 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)
/utopia/UTPA2-700.0.x/modules/bdma/hal/M7621/bdma/
H A DhalBDMA.c979 #define PMSLEEP_REG_BASE 0x0e00UL //0x000e00 macro
980 #define REG_PM_CPUX_SW_RSTZ (PMSLEEP_REG_BASE + 0x29*2)

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