1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2009-2010 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 #ifndef MHAL_XC_CONFIG_H 95 #define MHAL_XC_CONFIG_H 96 97 //------------------------------------------------------------------------------------------------- 98 // Monaco 99 //------------------------------------------------------------------------------------------------- 100 //------------------------------------------------------------------------------------------------- 101 // Chip Configuration 102 //------------------------------------------------------------------------------------------------- 103 #define MAX_XC_DEVICE_NUM (2) 104 #define MAX_XC_DEVICE0_OFFSET (0) 105 #define MAX_XC_DEVICE1_OFFSET (128) 106 107 #define MAX_WINDOW_NUM (2) 108 #define MAX_FRAME_NUM_IN_MEM (4) // Progressive 109 #define MAX_FIELD_NUM_IN_MEM (16) // Interlace 110 #define NUM_OF_DIGITAL_DDCRAM (1) 111 112 #define SCALER_LINE_BUFFER_MAX (4096UL) 113 #define MST_LINE_BFF_MAX MAX(4096, SCALER_LINE_BUFFER_MAX) 114 115 #define SUB_MAIN_LINEOFFSET_GUARD_BAND 0 116 #define SUB_SCALER_LINE_BUFFER_MAX 2048UL - SUB_MAIN_LINEOFFSET_GUARD_BAND 117 #define SUB_MST_LINE_BFF_MAX SUB_SCALER_LINE_BUFFER_MAX 118 119 #define MS_3D_LINE_BFF_MAX (2048UL) 120 121 // MIU Word (Bytes) 122 #define BYTE_PER_WORD (32) // MIU 128: 16Byte/W, MIU 256: 32Byte/W 123 #define OFFSET_PIXEL_ALIGNMENT (64) 124 #define LPLL_LOOPGAIN (32) //due to bound cale. 125 #define LVDS_MPLL_CLOCK_MHZ (432) 126 #define FRC_OFFSET_PIXEL_ALIGNMENT (128) 127 128 #define FRC_BYTE_PER_WORD 32 129 #define MCDI_BYTE_PER_WORD 32 130 131 //value for pipe vcnt and hcnt delay 132 #define FRC_PIPE_DELAY_VCNT_FRC 0x10 133 #define FRC_PIPE_DELAY_HCNT_FRC 0x140 134 #define FRC_PIPE_DELAY_VCNT_FSC_FHD 0x1D 135 #define FRC_PIPE_DELAY_HCNT_FSC_FHD 0x140 136 #define FRC_PIPE_DELAY_VCNT_FSC_4K 0x0B 137 #define FRC_PIPE_DELAY_HCNT_FSC_4K 0x140 138 139 140 #define DEFAULT_STEP_P 4 //conservative step value 141 #define DEFAULT_STEP_I ((DEFAULT_STEP_P*DEFAULT_STEP_P)/2) 142 #define STEP_P 2 //recommended step value -> more faster fpll(T3) 143 #define STEP_I ((STEP_P*STEP_P)/2) 144 #define IPGAIN_REFACTOR 5 145 146 #define F2_WRITE_LIMIT_EN BIT(31) //BK12_1b[15] 147 #define F2_WRITE_LIMIT_MIN BIT(30) //BK12_1b[14] 148 149 #define F1_WRITE_LIMIT_EN BIT(31) //BK12_5b[15] 150 #define F1_WRITE_LIMIT_MIN BIT(30) //BK12_5b[14] 151 152 #define F2_FRCM_WRITE_LIMIT_EN BIT(31) //BK32_1b[15] 153 #define F1_FRCM_WRITE_LIMIT_EN BIT(31) //BK32_5b[15] 154 155 #define F2_V_WRITE_LIMIT_EN BIT(15) //BK12_18[12] 156 #define F1_V_WRITE_LIMIT_EN BIT(15) //BK12_58[12] 157 158 #define F2_OPW_WRITE_LIMIT_EN BIT(31) //for UC 159 #define F2_OPW_WRITE_LIMIT_MIN BIT(30) //for UC 160 161 #define ADC_MAX_CLK (3500) 162 163 #define SUPPORTED_XC_INT ((1UL << SC_INT_DIPW) | \ 164 (1UL << SC_INT_VSINT) | \ 165 (1UL << SC_INT_F2_VTT_CHG) | \ 166 (1UL << SC_INT_F1_VTT_CHG) | \ 167 (1UL << SC_INT_F2_VS_LOSE) | \ 168 (1UL << SC_INT_F1_VS_LOSE) | \ 169 (1UL << SC_INT_F2_JITTER) | \ 170 (1UL << SC_INT_F1_JITTER) | \ 171 (1UL << SC_INT_F2_IPVS_SB) | \ 172 (1UL << SC_INT_F1_IPVS_SB) | \ 173 (1UL << SC_INT_F2_IPHCS_DET) | \ 174 (1UL << SC_INT_F1_IPHCS_DET) | \ 175 (1UL << SC_INT_F2_HTT_CHG) | \ 176 (1UL << SC_INT_F1_HTT_CHG) | \ 177 (1UL << SC_INT_F2_HS_LOSE) | \ 178 (1UL << SC_INT_F1_HS_LOSE) | \ 179 (1UL << SC_INT_F2_CSOG) | \ 180 (1UL << SC_INT_F1_CSOG) | \ 181 (1UL << SC_INT_F2_ATP_READY) | \ 182 (1UL << SC_INT_F1_ATP_READY)) 183 184 185 //These table definition is from SC_BK0 spec. 186 //Because some chip development is different, it need to check and remap when INT function is used 187 188 #define IRQ_INT_DIPW 0 189 #define IRQ_INT_START 3 190 #define IRQ_INT_RESERVED1 IRQ_INT_START 191 192 #define IRQ_INT_VSINT 4 193 #define IRQ_INT_F2_VTT_CHG 5 194 #define IRQ_INT_F1_VTT_CHG 6 195 #define IRQ_INT_F2_VS_LOSE 7 196 #define IRQ_INT_F1_VS_LOSE 8 197 #define IRQ_INT_F2_JITTER 9 198 #define IRQ_INT_F1_JITTER 10 199 #define IRQ_INT_F2_IPVS_SB 11 200 #define IRQ_INT_F1_IPVS_SB 12 201 #define IRQ_INT_F2_IPHCS_DET 13 202 #define IRQ_INT_F1_IPHCS_DET 14 203 204 #define IRQ_INT_PWM_RP_L_INT 15 205 #define IRQ_INT_PWM_FP_L_INT 16 206 #define IRQ_INT_F2_HTT_CHG 17 207 #define IRQ_INT_F1_HTT_CHG 18 208 #define IRQ_INT_F2_HS_LOSE 19 209 #define IRQ_INT_F1_HS_LOSE 20 210 #define IRQ_INT_PWM_RP_R_INT 21 211 #define IRQ_INT_PWM_FP_R_INT 22 212 #define IRQ_INT_F2_CSOG 23 213 #define IRQ_INT_F1_CSOG 24 214 #define IRQ_INT_F2_RESERVED2 25 215 #define IRQ_INT_F1_RESERVED2 26 216 #define IRQ_INT_F2_ATP_READY 27 217 #define IRQ_INT_F1_ATP_READY 28 218 #define IRQ_INT_F2_RESERVED3 29 219 #define IRQ_INT_F1_RESERVED3 30 220 221 //------------------------------------------------------------------------------------------------- 222 // Chip Feature 223 //------------------------------------------------------------------------------------------------- 224 /* 12 frame mode for progessive */ 225 #define _12FRAME_BUFFER_PMODE_SUPPORTED 1 226 /* 8 frame mode for progessive */ 227 #define _8FRAME_BUFFER_PMODE_SUPPORTED 1 228 /* 6 frame mode for progessive */ 229 #define _6FRAME_BUFFER_PMODE_SUPPORTED 1 230 /* 4 frame mode for progessive */ 231 #define _4FRAME_BUFFER_PMODE_SUPPORTED 1 232 /* 3 frame mode for progessive */ 233 #define _3FRAME_BUFFER_PMODE_SUPPORTED 1 234 /* change Vtt BK68 replace BK10 */ 235 #define PATCH_HW_VTT_LIMITATION 1 236 /* Vtt BK10 not be replaced, CHIP number after U2 */ 237 #define HW_VTT_LIMITATION_CHIPREV 1 238 /* Macan VE 2Pto1P HW PATCH*/ 239 #define PATCH_HW_VE_2Pto1P 1 240 /*Macan PIXSHIFT HW PATCH*/ 241 #define PATCH_HW_PIXSHIFT 1 242 /* 243 Field-packing ( Customized name ) 244 This is a feature in M10. M10 only needs one IPM buffer address. (Other chips need two or three 245 IPM buffer address). We show one of memory format for example at below. 246 247 Block : Y0 C0 L M Y1 C1 248 Each block contain 4 fields (F0 ~ F3) and each fields in one block is 64 bits 249 Y0 has 64 * 4 bits ( 8 pixel for each field ). 250 Y1 has 64 * 4 bits ( 8 pixel for each field ). 251 So, in this memory format, pixel alignment is 16 pixels (OFFSET_PIXEL_ALIGNMENT = 16). 252 For cropping, OPM address offset have to multiple 4. 253 */ 254 #define _FIELD_PACKING_MODE_SUPPORTED 1 255 256 #if (_FIELD_PACKING_MODE_SUPPORTED) 257 258 /* Linear mode */ 259 #define _LINEAR_ADDRESS_MODE_SUPPORTED 0 260 261 #else 262 /* Linear mode */ 263 #define _LINEAR_ADDRESS_MODE_SUPPORTED 1 264 265 #endif 266 267 #define SUPPORT_2_FRAME_MIRROR 0 268 269 /* Because fix loop_div, lpll initial set is different between singal port and dual port */ 270 #define _FIX_LOOP_DIV_SUPPORTED 1 271 272 // You can only enable ENABLE_8_FIELD_SUPPORTED or ENABLE_16_FIELD_SUPPORTED. (one of them) 273 // 16 field mode include 8 field configurion in it. ENABLE_8_FIELD_SUPPORTED is specital case in T7 274 #define ENABLE_8_FIELD_SUPPORTED 0 275 #define ENABLE_16_FIELD_SUPPORTED 1 276 #define ENABLE_OPM_WRITE_SUPPORTED 1 277 #define ENABLE_YPBPR_PRESCALING_TO_ORIGINAL 0 278 #define ENABLE_VD_PRESCALING_TO_DOT75 0 279 #define ENABLE_NONSTD_INPUT_MCNR 0 280 #define ENABLE_REGISTER_SPREAD 1 281 282 #define ENABLE_REQUEST_FBL 1 283 #define DELAY_LINE_SC_UP 7 284 #define DELAY_LINE_SC_DOWN 8 285 286 #define CHANGE_VTT_STEPS 1 287 #define CHANGE_VTT_DELAY 1 288 289 #define SUPPORT_IMMESWITCH 1 290 #define SUPPORT_DVI_AUTO_EQ 1 291 #define SUPPORT_MHL 0 292 #define SUPPORT_HDMI_RX_NEW_FEATURE 1 293 #define SUPPORT_DEVICE1 0 294 #define SUPPORT_SEAMLESS_ZAPPING 0 295 #define SUPPORT_OP2_TEST_PATTERN 1 296 #define SUPPORT_FRCM_MODE 0 297 #define SUPPORT_4K2K_PIP 1 298 #define SUPPORT_KERNEL_MLOAD 1 299 #define SUPPORT_KERNEL_DS 1 300 301 // Special frame lock means that the frame rates of input and output are the same in HW design spec. 302 #define SUPPORT_SPECIAL_FRAMELOCK FALSE 303 304 #define LD_ENABLE 0 // 1 305 #define FRC_INSIDE FALSE 306 #define FRC_IP_NUM_Passive 17 //FRC__NUM_FRC_Mapping_mode 307 308 // 480p and 576p have FPLL problem in HV mode. 309 // So only allow HV mode for 720P 310 #define ONLY_ALLOW_HV_MODE_FOR_720P 0 311 312 #define _ENABLE_SW_DS 0 313 #define DS_BUFFER_NUM_EX 6 314 #define DS_MAX_INDEX 6 315 316 #define ENABLE_64BITS_COMMAND 1 317 #define ENABLE_64BITS_SPREAD_MODE 1 //need enable ENABLE_64BITS_COMMAND first 318 //------------------------------------------------------------------------------------------------- 319 /// enable ENABLE_MLOAD_SAME_REG_COMBINE you can do: 320 /// MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_01_L, BIT(N), BIT(N)); 321 /// MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_01_L, BIT(M), BIT(M)); 322 /// MApi_XC_MLoad_Fire(); 323 //------------------------------------------------------------------------------------------------- 324 #define ENABLE_MLOAD_SAME_REG_COMBINE 1 325 326 #define IS_SUPPORT_64BITS_COMMAND(bEnable64bitsCmd, u32DeviceID) ((bEnable64bitsCmd == 1) && (u32DeviceID == 0)) 327 #define ENABLE_DS_4_BASEADDR_MODE 1 // need enable both ENABLE_64BITS_COMMAND and ENABLE_64BITS_SPREAD_MODE first 328 #define DS_CMD_LEN_64BITS 8 329 330 // T12, T13 cannot use IP_HDMI for HV mode 331 // We must use IP_HDMI for HV mode, otherwise 480i 576i will have color space proble,m 332 //Note: if use IP_HDMI, MApi_XC_GetDEWindow() cannot get value correctly 333 // and IP_HDMI is set in MApi_XC_SetInputSource(), so cannot change dynamically 334 // Thus, chip could use this flag to determine whether could do HV mode or not. 335 #define SUPPORT_IP_HDMI_FOR_HV_MODE 0 336 337 // version1: edison: 4k2k@mm :mvop->dip->gop->ursa; 4k2k@hdmi:hdmi->ursa 338 // version2: nike: 339 // version3: napoli: frc: double frc and width 340 // version4: monaco: frcm and 2p 341 // version5: clippers: 4k2k@60 MVOP directly output to HVSP 342 // version6: Monet/Maya/Manhattan: 343 // for Manhattan pip:1.SC1(1P) Htt = SC0(2P) Htt/2 344 // 2.if xc mute SC1 main, please mute SC0 sub. The same to mute color. 345 // 3.SC1 DE(bank 0x90) HStart = SC0 DE HStart/2, SC1 DE(bank 0x90) Width = SC0 DE Width/2 346 // 4.temp solution:SC0 DE VStart/Vend should add 6, so is SC1 DE Vstart/Vend 347 #define HW_DESIGN_4K2K_VER (6) 348 349 #define HW_DESIGN_3D_VER (3) 350 #define HW_2DTO3D_SUPPORT TRUE 351 #define HW_2DTO3D_VER (4) 352 #define HW_2DTO3D_BYTE_PER_WORD (32) 353 #define HW_2DTO3D_PATCH FALSE //a1 u01:2d to 3d hw bug 354 #define HW_2DTO3D_BLOCK_DR_BUF_SIZE (0x2200) 355 #define HW_2DTO3D_DD_BUF_SIZE (0xFF00) 356 #define ENABLE_GOP_T3DPATCH 357 358 //hw support fbl 3d or not. if support,can do SBS to LBL and SBS to SBS 359 #define HW_3D_SUPPORT_FBL TRUE 360 //M10, A2, J2 ,A5,A6,A3,Agate HW will automatic use IPM fetch's reg setting to alignment IPM fetch, so skip sw alignment 361 //and for mirror cbcr swap, need check IPM fetch to decide if need swap 362 #define HW_IPM_FETCH_ALIGNMENT TRUE 363 //hw support 2 line mode deinterlace for interlace or not 364 #define HW_2LINEMODE_DEINTERLACE_SUPPORT FALSE 365 #define HW_CLK_CTRL TRUE 366 #define SUPPORT_OSD_HSLVDS_PATH 1 367 //#define MLG_1024 368 #define SUPPORT_GAMMA_AUTODOWNLOAD 369 370 #define OSD_LAYER_NUM (5) 371 #define VIDEO_OSD_SWITCH_VER (2) 372 373 //#define FA_1920X540_OUTPUT 374 #define XC_SUPPORT_4K2K 1 375 376 // if H/W support 2p mode to achieve 600M HZ 377 #define XC_SUPPORT_2P_MODE TRUE 378 379 //HW support 2 step scaling 380 #define XC_SUPPORT_2STEP_SCALING 381 382 //device 1 is interlace out 383 #define XC_DEVICE1_IS_INTERLACE_OUT 0 384 385 //if H/W support force post-Vscalin-down in DS mode 386 #define HW_SUPPORT_FORCE_VSP_IN_DS_MODE TRUE 387 388 //if H/W support LPLL lock freqence not lock phase mode 389 #define HW_SUPPORT_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE TRUE 390 391 // if H/W support interlace output timing 392 #define HW_SUPPORT_INTERLACE_OUTPUT TRUE 393 394 // if H/W support 4k2k_60p output timing 395 #define HW_SUPPORT_4K2K_60P_OUTPUT TRUE 396 397 #define SUPPORT_MOD_ADBANK_SEPARATE 398 399 #define SUPPORT_FPLL_REFER_24MXTAL 400 401 // for 4K 0.5K 240Hz case, if input only 25fps, ivs:ovs = 5:48 case 402 #define SUPPORT_FPLL_DOUBLE_OVS 403 404 #define SUPPORT_HDMI20 1 405 406 #define LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE 1 407 408 /// for Chip bringup 409 #define ENABLE_CHIP_BRINGUP 410 #define PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB 0 // support pip&pop by multi sc ,such as sc1 support pip&pop 411 412 #define HW_4K2K_VIP_PEAKING_LIMITATION 0 413 414 #if (PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB == 0) 415 //#define ENABLE_TV_SC2_PQ 416 #endif 417 //#define MONACO_SC2_PATCH 418 419 #define XC_SUPPORT_CMA TRUE 420 421 #define XC_CMA_8MB 0x0800000 422 #define XC_CMA_10MB 0x0A00000 423 #define XC_CMA_12MB 0x0C00000 424 #define XC_CMA_15MB 0x0F00000 425 #define XC_CMA_16MB 0x1000000 426 #define XC_CMA_18MB 0x1200000 427 #define XC_CMA_19MB 0x1300000 428 #define XC_CMA_20MB 0x1400000 429 #define XC_CMA_22MB 0x1600000 430 #define XC_CMA_24MB 0x1800000 431 #define XC_CMA_32MB 0x2000000 432 #define XC_CMA_36MB 0x2400000 433 #define XC_CMA_30MB 0x1E00000 434 #define XC_CMA_40MB 0x2800000 435 #define XC_CMA_48MB 0x3000000 436 #define XC_CMA_64MB 0x4000000 437 #define XC_CMA_72MB 0x4800000 438 #define XC_CMA_96MB 0x6000000 439 440 #define XC_4K2K_WIDTH_MAX 4500 441 #define XC_4K2K_WIDTH_MIN 3000 442 #define XC_4K2K_HIGH_MAX 2500 443 #define XC_4K2K_HIGH_MIN 1900 444 445 #define XC_4K1K_WIDTH_MAX 4500 446 #define XC_4K1K_WIDTH_MIN 3000 447 #define XC_4K1K_HIGH_MAX 1300 448 #define XC_4K1K_HIGH_MIN 900 449 450 #define XC_4K_HALFK_WIDTH_MAX 4500 // 4K 0.5K 451 #define XC_4K_HALFK_WIDTH_MIN 3000 // 4K 0.5K 452 #define XC_4K_HALFK_HIGH_MAX 600 // 4K 0.5K 453 #define XC_4K_HALFK_HIGH_MIN 500 // 4K 0.5K 454 455 #define XC_2K2K_WIDTH_MAX 2300 456 #define XC_2K2K_WIDTH_MIN 1500 457 #define XC_2K2K_HIGH_MAX 2500 458 #define XC_2K2K_HIGH_MIN 1900 459 460 #define XC_FHD_WIDTH_MAX 2300 461 #define XC_FHD_WIDTH_MIN 1500 462 #define XC_FHD_HIGH_MAX 1300 463 #define XC_FHD_HIGH_MIN 900 464 465 #define XC_FRC_IPM_L 0x2C4C000 // 4096x2160x1.5x7/2 466 #define XC_FRC_IPM_R 0x2C4C000 // 4096x2160x1.5x7/2 467 #define XC_FRC_MEDS_L 0x084E400 // 2048x1080x0.75x7/2x1.5 468 #define XC_FRC_MEDS_R 0x084E400 // 2048x1080x0.75x7/2x1.5 469 #define XC_FRC_ME1_X1 0x0061080 // 8x135x32x11.5 470 #define XC_FRC_ME1_S1 0x0030840 // 8x135x32x23 471 #define XC_FRC_ME2_X2 0x02D7BC0 // 30x270x32x11.5 472 #define XC_FRC_ME2_Y2 0x00C2100 // 8x270x32x11.5 473 #define XC_FRC_ME2_F2 0x01B4A40 // 18x270x32x11.5 474 #define XC_FRC_ME2_LOGO 0x00C2100 // 8x270x32x11.5 475 #define XC_FRC_HR 0x01FA400 // 40x270x32x6 476 #define XC_FRC_HR_BUF23 0x02F7600 // 30x270x32x12 477 478 479 480 //------------------------------------------------------------------------------------------------- 481 // Register base 482 //------------------------------------------------------------------------------------------------- 483 484 // PM 485 #define REG_DDC_BASE 0x000400UL 486 #define REG_PM_SLP_BASE 0x000E00UL 487 #define REG_PM_GPIO_BASE 0x000F00UL 488 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung 489 #define REG_PAD_SAR_BASE 0x001400UL 490 #define REG_SCDC0_BASE 0x010200UL 491 #define REG_SCDC1_BASE 0x010300UL 492 #define REG_SCDC2_BASE 0x010400UL 493 #define REG_SCDC3_BASE 0x010500UL 494 #define REG_PM_TOP_BASE 0x001E00UL 495 #define REG_MHL_CBUS_BANK 0x001F00UL 496 #define REG_EFUSE_BASE 0x002000UL 497 #define REG_PM_MHL_CBUS_BANK 0x002F00UL 498 499 // NONPM 500 #define REG_MIU0_BASE 0x101200UL 501 #define REG_MIU0_EX_BASE 0x161500UL 502 #define REG_MIU0_ARBB_BASE 0x152000UL 503 #define REG_MIU1_BASE 0x100600UL 504 #define REG_MIU1_EX_BASE 0x162200UL 505 #define REG_MIU1_ARBB_BASE 0x152100UL 506 #define REG_MIU2_BASE 0x162000UL 507 #define REG_MIU2_EX_BASE 0x162300UL 508 #define REG_MIU2_ARBB_BASE 0x152200UL 509 510 #define REG_CLKGEN2_BASE 0x100A00UL 511 #define REG_CLKGEN0_BASE 0x100B00UL // 0x1E00 - 0x1EFF 512 #define REG_CHIP_BASE 0x101E00UL 513 #define REG_UHC0_BASE 0x102400UL 514 #define REG_UHC1_BASE 0x100D00UL 515 #define REG_ADC_ATOP_BASE 0x102500UL // 0x2500 - 0x25FF 516 #define REG_ADC_DTOP_BASE 0x102600UL // 0x2600 - 0x26EF 517 #define REG_ADC_CHIPTOP_BASE 0x101E00UL // 0x1E00 - 0x1EFF 518 #define REG_HDMI_BASE 0x102700UL // 0x2700 - 0x27FF 519 #define REG_CHIP_GPIO_BASE 0x102B00UL 520 #define REG_ADC_ATOPB_BASE 0x103D00UL // 0x3D00 - 0x3DFF 521 522 #define REG_HDMI2_BASE 0x101A00UL 523 #define REG_IPMUX_BASE 0x102E00UL 524 #define REG_MVOP_BASE 0x101400UL 525 #if ENABLE_REGISTER_SPREAD 526 #define REG_SCALER_BASE 0x130000UL 527 #else 528 #define REG_SCALER_BASE 0x102F00UL 529 #endif 530 #define REG_LPLL_BASE 0x103100UL 531 #define REG_MOD_BASE 0x103200UL 532 #define REG_PWM_BASE 0x13F400UL 533 #define REG_MOD_A_BASE 0x111E00UL 534 #define REG_AFEC_BASE 0x103500UL 535 #define REG_COMB_BASE 0x103600UL 536 537 #define REG_HDCPKEY_BASE 0x173800UL 538 #define REG_DVI_ATOP_BASE 0x110900UL 539 #define REG_DVI_DTOP_BASE 0x110A00UL 540 #define REG_DVI_EQ_BASE 0x110A80UL // EQ started from 0x80 541 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 542 #define REG_ADC_DTOPB_BASE 0x111200UL // ADC DTOPB 543 #define REG_DVI_ATOP1_BASE 0x113200UL 544 #define REG_DVI_DTOP1_BASE 0x113300UL 545 #define REG_DVI_EQ1_BASE 0x113380UL // EQ started from 0x80 546 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 547 #define REG_DVI_ATOP2_BASE 0x113400UL 548 #define REG_DVI_ATOP3_BASE 0x162F00UL 549 #define REG_DVI_DTOP2_BASE 0x113500UL 550 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 551 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 552 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving 553 #define REG_DVI_PS1_BASE 0x113640UL // DVI power saving1 554 #define REG_DVI_PS2_BASE 0x113680UL // DVI power saving2 555 #define REG_DVI_PS3_BASE 0x1136C0UL // DVI power saving3 556 #define REG_DVI_DTOP3_BASE 0x113700UL 557 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 558 #define REG_HDCP3_BASE 0x1137C0UL // HDCP started from 0xC0 559 560 #define REG_CHIP_ID_MAJOR 0x1ECC 561 #define REG_CHIP_ID_MINOR 0x1ECD 562 #define REG_CHIP_VERSION 0x1ECE 563 #define REG_CHIP_REVISION 0x1ECFUL 564 #define REG_CHIP_GPIO1_BASE 0x110300UL 565 566 #define REG_COMBO_PHY0_P0_BASE 0x170200UL 567 #define REG_COMBO_PHY1_P0_BASE 0x170300UL 568 #define REG_COMBO_PHY0_P1_BASE 0x170400UL 569 #define REG_COMBO_PHY1_P1_BASE 0x170500UL 570 #define REG_COMBO_PHY0_P2_BASE 0x170600UL 571 #define REG_COMBO_PHY1_P2_BASE 0x170700UL 572 #define REG_COMBO_PHY0_P3_BASE 0x170800UL 573 #define REG_COMBO_PHY1_P3_BASE 0x170900UL 574 575 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL 576 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL 577 #define REG_HDCP_DUAL_P0_BASE 0x171200UL 578 #define REG_DVI_DTOP_DUAL_P1_BASE 0x171300UL 579 #define REG_DVI_RSV_DUAL_P1_BASE 0x171400UL 580 #define REG_HDCP_DUAL_P1_BASE 0x171500UL 581 #define REG_DVI_DTOP_DUAL_P2_BASE 0x171600UL 582 #define REG_DVI_RSV_DUAL_P2_BASE 0x171700UL 583 #define REG_HDCP_DUAL_P2_BASE 0x171800UL 584 #define REG_DVI_DTOP_DUAL_P3_BASE 0x171900UL 585 #define REG_DVI_RSV_DUAL_P3_BASE 0x171A00UL 586 #define REG_HDCP_DUAL_P3_BASE 0x171B00UL 587 588 #define REG_HDMI_DUAL_0_BASE 0x173000UL 589 #define REG_HDMI2_DUAL_0_BASE 0x173100UL 590 #define REG_HDMI3_DUAL_0_BASE 0x173400UL 591 592 #define REG_COMBO_GP_TOP_BASE 0x173900UL 593 #define REG_SECURE_TZPC_BASE 0x173A00UL 594 595 //VE BANK 596 #define REG_VE0_BASE 0x103B00UL 597 598 ////////////////////////// FRC using //////////////////////////////// 599 #define REG_CLKGEN0_BASE 0x100B00UL 600 #define REG_CLKGEN1_BASE 0x103300UL 601 602 ///FRC Area 603 #define REG_FSC_BANK_BASE 0x140000UL // FSC 0x102C bank, direct bank is 0x1400 604 #define REG_FRC_BANK_BASE 0x400000UL 605 606 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 607 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 608 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 609 #define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 610 /////////////////////////////////////////////////////////////////// 611 612 // store bank 613 #define LPLL_BK_STORE \ 614 MS_U8 u8Bank; \ 615 u8Bank = MDrv_ReadByte(REG_LPLL_BASE) 616 617 // restore bank 618 #define LPLL_BK_RESTORE MDrv_WriteByte(REG_LPLL_BASE, u8Bank) 619 620 // switch bank 621 #define LPLL_BK_SWITCH(_x_) MDrv_WriteByte(REG_LPLL_BASE, _x_) 622 623 624 //------------------------------------------------------------------------------ 625 // Register configure 626 //------------------------------------------------------------------------------ 627 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out 628 #define CKG_DACA2_GATED BIT(0) 629 #define CKG_DACA2_INVERT BIT(1) 630 #define CKG_DACA2_MASK BMASK(3:2) 631 #define CKG_DACA2_VIF_CLK (0 << 2) 632 #define CKG_DACA2_VD_CLK (1 << 2) 633 #define CKG_DACA2_EXT_TEST_CLK (2 << 2) 634 #define CKG_DACA2_XTAL (3 << 2) 635 636 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out 637 #define CKG_DACB2_GATED BIT(0) 638 #define CKG_DACB2_INVERT BIT(1) 639 #define CKG_DACB2_MASK BMASK(3:2) 640 #define CKG_DACB2_VIF_CLK (0 << 2) 641 #define CKG_DACB2_VD_CLK (1 << 2) 642 #define CKG_DACB2_EXT_TEST_CLK (2 << 2) 643 #define CKG_DACB2_XTAL (3 << 2) 644 645 #define REG_CKG_EDCLK_F1 (REG_CLKGEN0_BASE + 0x9C ) // EDCLK_F1, CLK_GEN0_4E_L 646 #define CKG_EDCLK_F1_GATED BIT(0) 647 #define CKG_EDCLK_F1_INVERT BIT(1) 648 #define CKG_EDCLK_F1_MASK BMASK(4:2) 649 #define CKG_EDCLK_F1_ADC (0 << 2) 650 #define CKG_EDCLK_F1_DVI (1 << 2) 651 #define CKG_EDCLK_F1_345MHZ (2 << 2) 652 #define CKG_EDCLK_F1_216MHZ (3 << 2) 653 #define CKG_EDCLK_F1_192MHZ (4 << 2) 654 #define CKG_EDCLK_F1_240MHZ (5 << 2) 655 #define CKG_EDCLK_F1_320MHZ (6 << 2) 656 #define CKG_EDCLK_F1_XTAL (7 << 2) 657 658 #define REG_CKG_EDCLK_F2 (REG_CLKGEN0_BASE + 0x9D ) // EDCLK_F2, CLK_GEN0_4E_L 659 #define CKG_EDCLK_F2_GATED BIT(0) 660 #define CKG_EDCLK_F2_INVERT BIT(1) 661 #define CKG_EDCLK_F2_MASK BMASK(4:2) 662 #define CKG_EDCLK_F2_ADC (0 << 2) 663 #define CKG_EDCLK_F2_DVI (1 << 2) 664 #define CKG_EDCLK_F2_345MHZ (2 << 2) 665 #define CKG_EDCLK_F2_216MHZ (3 << 2) 666 #define CKG_EDCLK_F2_192MHZ (4 << 2) 667 #define CKG_EDCLK_F2_240MHZ (5 << 2) 668 #define CKG_EDCLK_F2_320MHZ (6 << 2) 669 #define CKG_EDCLK_F2_XTAL (7 << 2) 670 671 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) 672 #define CKG_FMCLK_GATED BIT(0) 673 #define CKG_FMCLK_INVERT BIT(1) 674 #define CKG_FMCLK_MASK BMASK(3:2) 675 #define CKG_FMCLK_FCLK (0 << 2) 676 #define CKG_FMCLK_MIU_256 (1 << 2) 677 #define CKG_FMCLK_MIU_128 (2 << 2) 678 679 #define REG_CKG_SC_ROT (REG_CLKGEN0_BASE + 0xFF ) 680 #define CKG_SC_ROT_GATED BIT(0) 681 #define CKG_SC_ROT_INVERT BIT(1) 682 #define CKG_SC_ROT_MASK BMASK(3:2) 683 #define CKG_SC_ROT_MIU_256 (0 << 2) 684 #define CKG_SC_ROT_MIU_128 (1 << 2) 685 686 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 687 #define CKG_FICLK_F1_GATED BIT(0) 688 #define CKG_FICLK_F1_INVERT BIT(1) 689 #define CKG_FICLK_F1_MASK BMASK(3:2) 690 #define CKG_FICLK_F1_IDCLK1 (0 << 2) 691 #define CKG_FICLK_F1_FLK (1 << 2) 692 //#define CKG_FICLK_F1_XTAL (3 << 2) 693 694 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // for Monaco, this CLK is for VE using, not for FLCIK, and should set 0x00 for VE 695 #define CKG_FICLK_F2_GATED BIT(0) 696 #define CKG_FICLK_F2_INVERT BIT(1) 697 #define CKG_FICLK_F2_MASK BMASK(3:2) 698 #define CKG_FICLK_F2_IDCLK2 (0 << 2) 699 #define CKG_FICLK_F2_FLK (0 << 2) 700 //#define CKG_FICLK_F2_XTAL (3 << 2) 701 702 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 703 #define CKG_FICLK2_F2_GATED BIT(4) 704 #define CKG_FICLK2_F2_INVERT BIT(5) 705 #define CKG_FICLK2_F2_MASK BMASK(7:6) 706 #define CKG_FICLK2_F2_IDCLK2 (0 << 6) 707 #define CKG_FICLK2_F2_FCLK (1 << 6) 708 709 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk 710 #define CKG_FCLK_GATED BIT(0) 711 #define CKG_FCLK_INVERT BIT(1) 712 #define CKG_FCLK_MASK BMASK(4:2) 713 #define CKG_FCLK_170MHZ (0 << 2) 714 #define CKG_FCLK_CLK_MIU (1 << 2) 715 #define CKG_FCLK_345MHZ (2 << 2) 716 #define CKG_FCLK_216MHZ (3 << 2) 717 #define CKG_FCLK_192MHZ (4 << 2) 718 #define CKG_FCLK_240MHZ (5 << 2) 719 #define CKG_FCLK_320MHZ (6 << 2) 720 #define CKG_FCLK_XTAL (7 << 2) 721 #define CKG_FCLK_XTAL_ CKG_FCLK_XTAL//(8 << 2) for A5 no XTAL 722 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ 723 724 #define REG_CKG_ODCLK (REG_CLKGEN0_BASE + 0xA6 ) // output dot clock, usually select LPLL, select XTAL when debug 725 #define CKG_ODCLK_GATED BIT(0) 726 #define CKG_ODCLK_INVERT BIT(1) 727 #define CKG_ODCLK_MASK BMASK(5:2) 728 #define CKG_ODCLK_SC_PLL (0 << 2) 729 #define CKG_ODCLK_LPLL_DIV2 (1 << 2) 730 #define CKG_ODCLK_27M (2 << 2) 731 #define CKG_ODCLK_CLK_LPLL (3 << 2) 732 //#define CKG_ODCLK_XTAL (8 << 2) 733 734 #define REG_CKG_IDCLK0 (REG_CLKGEN0_BASE + 0xA8 ) // off-line detect idclk 735 #define CKG_IDCLK0_GATED BIT(0) 736 #define CKG_IDCLK0_INVERT BIT(1) 737 #define CKG_IDCLK0_MASK BMASK(5:2) 738 #define CKG_IDCLK0_CLK_ADC (0 << 2) 739 #define CKG_IDCLK0_CLK_DVI (1 << 2) 740 #define CKG_IDCLK0_CLK_VD (2 << 2) 741 #define CKG_IDCLK0_CLK_DC0 (3 << 2) 742 #define CKG_IDCLK0_ODCLK (4 << 2) 743 #define CKG_IDCLK0_0 (5 << 2) 744 #define CKG_IDCLK0_CLK_VD_ADC (6 << 2) 745 #define CKG_IDCLK0_00 (7 << 2) // same as 5 --> also is 0 746 #define CKG_IDCLK0_XTAL CKG_IDCLK0_ODCLK//(8 << 2) for A5 no XTAL, select as OD 747 748 #define REG_CKG_IDCLK1 (REG_CLKGEN0_BASE + 0xA9 ) // sub main window idclk 749 #define CKG_IDCLK1_GATED BIT(0) 750 #define CKG_IDCLK1_INVERT BIT(1) 751 #define CKG_IDCLK1_MASK BMASK(5:2) 752 #define CKG_IDCLK1_CLK_ADC (0 << 2) 753 #define CKG_IDCLK1_CLK_DVI (1 << 2) 754 #define CKG_IDCLK1_CLK_VD (2 << 2) 755 #define CKG_IDCLK1_CLK_DC0 (3 << 2) 756 #define CKG_IDCLK1_ODCLK (4 << 2) 757 #define CKG_IDCLK1_0 (5 << 2) 758 #define CKG_IDCLK1_CLK_VD_ADC (6 << 2) 759 #define CKG_IDCLK1_00 (7 << 2) // same as 5 --> also is 0 760 #define CKG_IDCLK1_XTAL CKG_IDCLK1_ODCLK//(8 << 2) for A5 no XTAL,select as OD 761 762 #define REG_CKG_PRE_IDCLK1 (REG_CLKGEN0_BASE + 0xBC ) // pre-main window idclk 763 #define CKG_PRE_IDCLK1_MASK BMASK(5:3) 764 #define CKG_PRE_IDCLK1_CLK_ADC (0 << 3) 765 #define CKG_PRE_IDCLK1_CLK_DVI (1 << 3) 766 #define CKG_PRE_IDCLK1_CLK_MHL (2 << 3) 767 768 #define REG_CKG_IDCLK2 (REG_CLKGEN0_BASE + 0xAA ) // main window idclk 769 #define CKG_IDCLK2_GATED BIT(0) 770 #define CKG_IDCLK2_INVERT BIT(1) 771 #define CKG_IDCLK2_MASK BMASK(5:2) 772 #define CKG_IDCLK2_CLK_ADC (0 << 2) 773 #define CKG_IDCLK2_CLK_DVI (1 << 2) 774 #define CKG_IDCLK2_CLK_VD (2 << 2) 775 #define CKG_IDCLK2_CLK_DC0 (3 << 2) 776 #define CKG_IDCLK2_CLK_ADC2 (4 << 2) 777 #define CKG_IDCLK2_0 (5 << 2) 778 #define CKG_IDCLK2_00 (6 << 2) 779 #define CKG_IDCLK2_ODCLK (7 << 2) // same as 5 --> also is 0 780 #define CKG_IDCLK2_CLK_SUB_DC0 (8 << 2) 781 #define CKG_IDCLK2_CLK_ADC3 (9 << 2) 782 #define CKG_IDCLK2_ODCLK2 (10 << 2) 783 #define CKG_IDCLK2_CLKMHL (11 << 2) 784 #define CKG_IDCLK2_XTAL CKG_IDCLK2_ODCLK//(8 << 2)no XTAL select as OD 785 786 #define REG_CKG_PRE_IDCLK2 (REG_CLKGEN0_BASE + 0xBC ) // pre-main window idclk 787 #define CKG_PRE_IDCLK2_MASK BMASK(8:6) 788 #define CKG_PRE_IDCLK2_CLK_ADC (0 << 6) 789 #define CKG_PRE_IDCLK2_CLK_DVI (1 << 6) 790 #define CKG_PRE_IDCLK2_CLK_MHL (2 << 6) 791 792 #define REG_CKG_IDCLK3 (REG_CLKGEN0_BASE + 0xB2 ) 793 #define CKG_IDCLK3_GATED BIT(0) 794 #define CKG_IDCLK3_INVERT BIT(1) 795 #define CKG_IDCLK3_MASK BMASK(5:2) 796 #define CKG_IDCLK3_CLK_ADC (0 << 2) 797 #define CKG_IDCLK3_CLK_DVI (1 << 2) 798 #define CKG_IDCLK3_CLK_VD (2 << 2) 799 #define CKG_IDCLK3_CLK_DC0 (3 << 2) 800 #define CKG_IDCLK3_ODCLK (4 << 2) 801 #define CKG_IDCLK3_0 (5 << 2) 802 #define CKG_IDCLK3_CLK_VD_ADC (6 << 2) 803 #define CKG_IDCLK3_00 (7 << 2) // same as 5 --> also is 0 804 #define CKG_IDCLK3_XTAL (8 << 2) 805 806 #define REG_CKG_PRE_IDCLK3 (REG_CLKGEN0_BASE + 0xBC ) 807 #define CKG_PRE_IDCLK3_MASK BMASK(11:9) 808 #define CKG_PRE_IDCLK3_CLK_ADC (0 << 9) 809 #define CKG_PRE_IDCLK3_CLK_DVI (1 << 9) 810 #define CKG_PRE_IDCLK3_CLK_MHL (2 << 9) 811 812 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + 0xBE ) 813 #define CKG_PDW0_GATED BIT(0) 814 #define CKG_PDW0_INVERT BIT(1) 815 #define CKG_PDW0_MASK BMASK(4:2) 816 #define CKG_PDW0_CLK_ADC (0 << 2) 817 #define CKG_PDW0_CLK_DVI (1 << 2) 818 #define CKG_PDW0_CLK_VD (2 << 2) 819 #define CKG_PDW0_CLK_DC0 (3 << 2) 820 #define CKG_PDW0_ODCLK (4 << 2) 821 #define CKG_PDW0_0 (5 << 2) 822 #define CKG_PDW0_CLK_VD_ADC (6 << 2) 823 #define CKG_PDW0_00 (7 << 2) // same as 5 --> also is 0 824 #define CKG_PDW0_XTAL (8 << 2) 825 826 #define REG_CKG_PDW1 (REG_CLKGEN0_BASE + 0xBF ) 827 #define CKG_PDW1_GATED BIT(0) 828 #define CKG_PDW1_INVERT BIT(1) 829 #define CKG_PDW1_MASK BMASK(4:2) 830 #define CKG_PDW1_CLK_ADC (0 << 2) 831 #define CKG_PDW1_CLK_DVI (1 << 2) 832 #define CKG_PDW1_CLK_VD (2 << 2) 833 #define CKG_PDW1_CLK_DC0 (3 << 2) 834 #define CKG_PDW1_ODCLK (4 << 2) 835 #define CKG_PDW1_0 (5 << 2) 836 #define CKG_PDW1_CLK_VD_ADC (6 << 2) 837 #define CKG_PDW1_00 (7 << 2) // same as 5 --> also is 0 838 #define CKG_PDW1_XTAL (8 << 2) 839 840 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) 841 #define CKG_OSDC_GATED BIT(0) 842 #define CKG_OSDC_INVERT BIT(1) 843 #define CKG_OSDC_MASK BMASK(3:2) 844 #define CKG_OSDC_CLK_LPLL_OSD (0 << 2) 845 846 #define REG_DE_ONLY_F3 (REG_CLKGEN0_BASE + 0xA0 ) 847 #define DE_ONLY_F3_MASK BIT(3) 848 849 #define REG_DE_ONLY_F2 (REG_CLKGEN0_BASE + 0xA0 ) 850 #define DE_ONLY_F2_MASK BIT(2) 851 852 #define REG_DE_ONLY_F1 (REG_CLKGEN0_BASE + 0xA0 ) 853 #define DE_ONLY_F1_MASK BIT(1) 854 855 #define REG_DE_ONLY_F0 (REG_CLKGEN0_BASE + 0xA0 ) 856 #define DE_ONLY_F0_MASK BIT(0) 857 858 859 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96) 860 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42) 861 862 #define REG_CLKGEN0_50_L (REG_CLKGEN0_BASE + 0xA0) 863 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) 864 #define REG_CLKGEN0_57_L (REG_CLKGEN0_BASE + 0xAE) 865 866 //MVOP 8bit address 867 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76) 868 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80) 869 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82) 870 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84) 871 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86) 872 #define REG_MVOP_4K2K_60_2P (REG_MVOP_BASE + (0x53<<1)) 873 #define GOP_MVOP_2P_EN_BIT BIT(1) 874 875 //VE 8bit address 876 #define REG_VE_ENABLE (REG_VE0_BASE + 0x00) 877 #define VE_EN_BIT BIT(0) 878 #define REG_VE_DAMMY_B (REG_VE0_BASE + 0x16) 879 880 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 ) 881 #define CKG_S2_MECLK_GATED BIT(0) 882 #define CKG_S2_MECLK_INVERT BIT(1) 883 #define CKG_S2_MECLK_MASK BMASK(5:2) 884 885 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 ) 886 #define CKG_S2_MGCLK_GATED BIT(0) 887 #define CKG_S2_MGCLK_INVERT BIT(1) 888 #define CKG_S2_MGCLK_MASK BMASK(5:2) 889 890 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) 891 #define CKG_S2_GOP_HDR_GATED BIT(0) 892 #define CKG_S2_GOP_HDR_INVERT BIT(1) 893 #define CKG_S2_GOP_HDR_MASK BMASK(5:2) 894 #define CKG_S2_GOP_HDR_ODCLK (0 << 2) 895 #define CKG_S2_GOP_HDR_EDCLK (1 << 2) 896 897 //// for SC2, at REG_CLKGEN2_BASE 898 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 ) 899 #define CKG_S2_FICLK_F1_GATED BIT(0) 900 #define CKG_S2_FICLK_F1_INVERT BIT(1) 901 #define CKG_S2_FICLK_F1_MASK BMASK(3:2) 902 #define CKG_S2_FICLK_F1_IDCLK1 (0 << 2) 903 #define CKG_S2_FICLK_F1_FLK (1 << 2) 904 905 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 ) 906 #define CKG_S2_FICLK_F2_GATED BIT(0) 907 #define CKG_S2_FICLK_F2_INVERT BIT(1) 908 #define CKG_S2_FICLK_F2_MASK BMASK(3:2) 909 #define CKG_S2_FICLK_F2_IDCLK2 (0 << 2) 910 #define CKG_S2_FICLK_F2_FLK (1 << 2) 911 912 #define REG_CKG_S2_FICLK2_F2 (REG_SCALER_BASE + REG_SC_BKBF_20_H) 913 #define CKG_S2_FICLK2_F2_GATED BIT(0) 914 #define CKG_S2_FICLK2_F2_INVERT BIT(1) 915 #define CKG_S2_FICLK2_F2_MASK BMASK(3:2) 916 #define CKG_S2_FICLK2_F2_IDCLK2 (0 << 2) // v prescaling 917 #define CKG_S2_FICLK2_F2_FCLK (1 << 2) // normal 918 #define CKG_S2_FICLK2_F2_MIUCLK (2 << 2) // DIP case 919 920 #define REG_CKG_S2_FCLK (REG_CLKGEN0_BASE+ 0xAF ) // after memory, before fodclk 921 #define CKG_S2_FCLK_GATED BIT(0) 922 #define CKG_S2_FCLK_INVERT BIT(1) 923 #define CKG_S2_FCLK_MASK BMASK(4:2) 924 #define CKG_S2_FCLK_172MHZ (0 << 2) 925 #define CKG_S2_FCLK_CLK_MIU (1 << 2) 926 #define CKG_S2_FCLK_345MHZ (2 << 2) 927 #define CKG_S2_FCLK_216MHZ (3 << 2) 928 #define CKG_S2_FCLK_192MHZ (4 << 2) 929 #define CKG_S2_FCLK_240MHZ (5 << 2) 930 #define CKG_S2_FCLK_320MHZ (6 << 2) 931 #define CKG_S2_FCLK_XTAL (7 << 2) 932 #define CKG_S2_FCLK_DEFAULT CKG_S2_FCLK_320MHZ 933 934 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 ) 935 #define CKG_S2_FODCLK_GATED BIT(0) 936 #define CKG_S2_FODCLK_INVERT BIT(1) 937 #define CKG_S2_FODCLK_CLK_ODCLK (0 << 2) 938 #define CKG_S2_FODCLK_CLK_MIU (1 << 2) 939 940 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 ) 941 #define CKG_S2_ODCLK_GATED BIT(0) 942 #define CKG_S2_ODCLK_INVERT BIT(1) 943 #define CKG_S2_ODCLK_MASK BMASK(3:2) 944 #define CKG_S2_ODCLK_SYN_CLK (0 << 2) 945 #define CKG_S2_ODCLK_LPLL_DIV2 (1 << 2) 946 #define CKG_S2_ODCLK_27M (2 << 2) 947 #define CKG_S2_ODCLK_CLK_LPLL (3 << 2) 948 949 #define REG_CKG_S2_IDCLK0 (REG_CLKGEN2_BASE + 0xC8 ) // off-line detect idclk 950 #define CKG_S2_IDCLK0_GATED BIT(0) 951 #define CKG_S2_IDCLK0_INVERT BIT(1) 952 #define CKG_S2_IDCLK0_MASK BMASK(5:2) 953 #define CKG_S2_IDCLK0_CLK_ADC (0 << 2) 954 #define CKG_S2_IDCLK0_CLK_DVI (1 << 2) 955 #define CKG_S2_IDCLK0_CLK_VD (2 << 2) 956 #define CKG_S2_IDCLK0_CLK_DC0 (3 << 2) 957 #define CKG_S2_IDCLK0_CLK_ADC2 (4 << 2) 958 #define CKG_S2_IDCLK0_0 (5 << 2) 959 #define CKG_S2_IDCLK0_00 (6 << 2) 960 #define CKG_S2_IDCLK0_ODCLK (7 << 2) 961 #define CKG_S2_IDCLK0_CLK_SUB_DC0 (8 << 2) 962 #define CKG_S2_IDCLK0_CLK_ADC3 (9 << 2) 963 #define CKG_S2_IDCLK0_ODCLK2 (10<< 2) 964 #define CKG_S2_IDCLK0_MHL (13<< 2) 965 #define CKG_S2_IDCLK0_XTAL CKG_S2_IDCLK0_ODCLK 966 967 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk 968 #define CKG_S2_IDCLK1_GATED BIT(0) 969 #define CKG_S2_IDCLK1_INVERT BIT(1) 970 #define CKG_S2_IDCLK1_MASK BMASK(5:2) 971 #define CKG_S2_IDCLK1_CLK_ADC (0 << 2) 972 #define CKG_S2_IDCLK1_CLK_DVI (1 << 2) 973 #define CKG_S2_IDCLK1_CLK_VD (2 << 2) 974 #define CKG_S2_IDCLK1_CLK_DC0 (3 << 2) 975 #define CKG_S2_IDCLK1_CLK_ADC2 (4 << 2) 976 #define CKG_S2_IDCLK1_0 (5 << 2) 977 #define CKG_S2_IDCLK1_00 (6 << 2) 978 #define CKG_S2_IDCLK1_ODCLK (7 << 2) 979 #define CKG_S2_IDCLK1_CLK_SUB_DC0 (8 << 2) 980 #define CKG_S2_IDCLK1_CLK_ADC3 (9 << 2) 981 #define CKG_S2_IDCLK1_ODCLK2 (10<< 2) 982 #define CKG_S2_IDCLK1_MHL (13<< 2) 983 #define CKG_S2_IDCLK1_XTAL CKG_S2_IDCLK1_ODCLK 984 985 #define REG_CKG_S2_IDCLK2 (REG_CLKGEN2_BASE + 0xCA ) // off-line detect idclk 986 #define CKG_S2_IDCLK2_GATED BIT(0) 987 #define CKG_S2_IDCLK2_INVERT BIT(1) 988 #define CKG_S2_IDCLK2_MASK BMASK(5:2) 989 #define CKG_S2_IDCLK2_CLK_ADC (0 << 2) 990 #define CKG_S2_IDCLK2_CLK_DVI (1 << 2) 991 #define CKG_S2_IDCLK2_CLK_VD (2 << 2) 992 #define CKG_S2_IDCLK2_CLK_DC0 (3 << 2) 993 #define CKG_S2_IDCLK2_CLK_ADC2 (4 << 2) 994 #define CKG_S2_IDCLK2_0 (5 << 2) 995 #define CKG_S2_IDCLK2_00 (6 << 2) 996 #define CKG_S2_IDCLK2_ODCLK (7 << 2) 997 #define CKG_S2_IDCLK2_CLK_SUB_DC0 (8 << 2) 998 #define CKG_S2_IDCLK2_CLK_ADC3 (9 << 2) 999 #define CKG_S2_IDCLK2_ODCLK2 (10<< 2) 1000 #define CKG_S2_IDCLK2_MHL (13<< 2) 1001 #define CKG_S2_IDCLK2_XTAL CKG_S2_IDCLK2_ODCLK 1002 1003 #define REG_CKG_S2_IDCLK3 (REG_CLKGEN2_BASE + 0xD2 ) // off-line detect idclk 1004 #define CKG_S2_IDCLK3_ATED BIT(0) 1005 #define CKG_S2_IDCLK3_INVERT BIT(1) 1006 #define CKG_S2_IDCLK3_MASK BMASK(5:2) 1007 #define CKG_S2_IDCLK3_CLK_ADC (0 << 2) 1008 #define CKG_S2_IDCLK3_CLK_DVI (1 << 2) 1009 #define CKG_S2_IDCLK3_CLK_VD (2 << 2) 1010 #define CKG_S2_IDCLK3_CLK_DC0 (3 << 2) 1011 #define CKG_S2_IDCLK3_CLK_ADC2 (4 << 2) 1012 #define CKG_S2_IDCLK3_0 (5 << 2) 1013 #define CKG_S2_IDCLK3_00 (6 << 2) 1014 #define CKG_S2_IDCLK3_ODCLK (7 << 2) 1015 #define CKG_S2_IDCLK3_CLK_SUB_DC0 (8 << 2) 1016 #define CKG_S2_IDCLK3_CLK_ADC3 (9 << 2) 1017 #define CKG_S2_IDCLK3_ODCLK2 (10<< 2) 1018 #define CKG_S2_IDCLK3_MHL (13<< 2) 1019 #define CKG_S2_IDCLK3_XTAL CKG_S2_IDCLK3_ODCLK 1020 1021 1022 #define REG_S2_DE_ONLY_F3 (REG_CLKGEN2_BASE + 0xC0 ) 1023 #define S2_DE_ONLY_F3_MASK BIT(3) 1024 1025 #define REG_S2_DE_ONLY_F2 (REG_CLKGEN2_BASE + 0xC0 ) 1026 #define S2_DE_ONLY_F2_MASK BIT(2) 1027 1028 #define REG_S2_DE_ONLY_F1 (REG_CLKGEN2_BASE + 0xC0 ) 1029 #define S2_DE_ONLY_F1_MASK BIT(1) 1030 1031 #define REG_S2_DE_ONLY_F0 (REG_CLKGEN2_BASE + 0xC0 ) 1032 #define S2_DE_ONLY_F0_MASK BIT(0) 1033 1034 //// 1035 #define CLK_SRC_IDCLK2 0 1036 #define CLK_SRC_FCLK 1 1037 #define CLK_SRC_XTAL 3 1038 1039 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46) 1040 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66) 1041 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86) 1042 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6) 1043 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06) 1044 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26) 1045 #define MIU0_G6_REQUEST_MASK (REG_MIU0_ARBB_BASE + 0x06) 1046 1047 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46) 1048 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66) 1049 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86) 1050 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6) 1051 #define MIU1_G4_REQUEST_MASK (REG_MIU1_EX_BASE + 0x06) 1052 #define MIU1_G5_REQUEST_MASK (REG_MIU1_EX_BASE + 0x26) 1053 #define MIU1_G6_REQUEST_MASK (REG_MIU1_ARBB_BASE + 0x06) 1054 1055 #define MIU2_G0_REQUEST_MASK (REG_MIU2_BASE + 0x46) 1056 #define MIU2_G1_REQUEST_MASK (REG_MIU2_BASE + 0x66) 1057 #define MIU2_G2_REQUEST_MASK (REG_MIU2_BASE + 0x86) 1058 #define MIU2_G3_REQUEST_MASK (REG_MIU2_BASE + 0xA6) 1059 #define MIU2_G4_REQUEST_MASK (REG_MIU2_EX_BASE + 0x06) 1060 #define MIU2_G5_REQUEST_MASK (REG_MIU2_EX_BASE + 0x26) 1061 #define MIU2_G6_REQUEST_MASK (REG_MIU2_ARBB_BASE + 0x06) 1062 1063 #define MIU_SC_G0REQUEST_MASK (0x0000) 1064 #define MIU_SC_G1REQUEST_MASK (0x0070) 1065 #define MIU_SC_G2REQUEST_MASK (0x0000) 1066 #define MIU_SC_G3REQUEST_MASK (0x0000) 1067 #define MIU_SC_G4REQUEST_MASK (0x0000) 1068 #define MIU_SC_G5REQUEST_MASK (0x0000) 1069 #define MIU_SC_G6REQUEST_MASK (0xF403) 1070 1071 ////////////////////////// FRC using //////////////////////////////// 1072 1073 #define MIU_FRC_G0REQUEST_MASK (0x0000) 1074 #define MIU_FRC_G1REQUEST_MASK (0x0000) 1075 #define MIU_FRC_G2REQUEST_MASK (0x0000) 1076 #define MIU_FRC_G3REQUEST_MASK (0x0000) 1077 #define MIU_FRC_G4REQUEST_MASK (0x0000) 1078 #define MIU_FRC_G5REQUEST_MASK (0x7FFF) 1079 #define MIU_FRC_G6REQUEST_MASK (0x0000) 1080 1081 1082 1083 /////////////////////////////////////////////////////////////////// 1084 1085 #define IP_DE_HSTART_MASK (0x1FFF) //BK_01_13 BK_03_13 1086 #define IP_DE_HEND_MASK (0x1FFF) //BK_01_15 BK_03_15 1087 #define IP_DE_VSTART_MASK (0x1FFF) //BK_01_12 BK_03_12 1088 #define IP_DE_VEND_MASK (0x1FFF) //BK_01_14 BK_03_14 1089 1090 #define VOP_DE_HSTART_MASK (0x3FFF) //BK_10_04 1091 #define VOP_DE_HEND_MASK (0x3FFF) //BK_10_05 1092 #define VOP_DE_VSTART_MASK (0x1FFF) //BK_10_06 1093 #define VOP_DE_VEND_MASK (0x1FFF) //BK_10_07 1094 1095 #define VOP_VTT_MASK (0x1FFF) //BK_10_0D 1096 #define VOP_HTT_MASK (0x3FFF) //BK_10_0C 1097 1098 #define VOP_VSYNC_END_MASK (0x1FFF) //BK_10_03 1099 #define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08 1100 #define VOP_DISPLAY_HEND_MASK (0x3FFF) //BK_10_09 1101 #define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A 1102 #define VOP_DISPLAY_VEND_MASK (0x1FFF) //BK_10_0B 1103 1104 1105 #define HW_DESIGN_LD_VER (2) 1106 1107 #define FPLL_THRESH_MODE_SUPPORT 0 1108 1109 #define ADC_EFUSE_IN_MBOOT 1110 1111 #define ADC_CENTER_GAIN 0x1000 1112 #define ADC_CENTER_OFFSET 0x0800 1113 #define ADC_GAIN_BIT_CNT 14 1114 #define ADC_OFFSET_BIT_CNT 13 1115 1116 #define ADC_VGA_DEFAULT_GAIN_R 0x1000 1117 #define ADC_VGA_DEFAULT_GAIN_G 0x1000 1118 #define ADC_VGA_DEFAULT_GAIN_B 0x1000 1119 #define ADC_VGA_DEFAULT_OFFSET_R 0x0000 1120 #define ADC_VGA_DEFAULT_OFFSET_G 0x0000 1121 #define ADC_VGA_DEFAULT_OFFSET_B 0x0000 1122 #define ADC_YPBPR_DEFAULT_GAIN_R 0x1212 1123 #define ADC_YPBPR_DEFAULT_GAIN_G 0x11AA 1124 #define ADC_YPBPR_DEFAULT_GAIN_B 0x1212 1125 #define ADC_YPBPR_DEFAULT_OFFSET_R 0x0800 1126 #define ADC_YPBPR_DEFAULT_OFFSET_G 0x0100 1127 #define ADC_YPBPR_DEFAULT_OFFSET_B 0x0800 1128 #define ADC_SCART_DEFAULT_GAIN_R 0x1000 1129 #define ADC_SCART_DEFAULT_GAIN_G 0x1000 1130 #define ADC_SCART_DEFAULT_GAIN_B 0x1000 1131 #define ADC_SCART_DEFAULT_OFFSET_R 0x0100 1132 #define ADC_SCART_DEFAULT_OFFSET_G 0x0100 1133 #define ADC_SCART_DEFAULT_OFFSET_B 0x0100 1134 1135 /////////////////////////////////////////////// 1136 // Enable Hardware auto gain/offset 1137 #define ADC_HARDWARE_AUTOOFFSET_RGB ENABLE 1138 #define ADC_HARDWARE_AUTOOFFSET_YPBPR ENABLE 1139 #define ADC_HARDWARE_AUTOOFFSET_SCARTRGB ENABLE 1140 #define ADC_HARDWARE_AUTOGAIN_SUPPORTED ENABLE 1141 #define ADC_VGA_FIXED_GAIN_R 0x1796 1142 #define ADC_VGA_FIXED_GAIN_G 0x1796 1143 #define ADC_VGA_FIXED_GAIN_B 0x1796 1144 #define ADC_VGA_FIXED_OFFSET_R 0x0000 1145 #define ADC_VGA_FIXED_OFFSET_G 0x0000 1146 #define ADC_VGA_FIXED_OFFSET_B 0x0000 1147 #define ADC_YPBPR_FIXED_GAIN_R 0x14B7 1148 #define ADC_YPBPR_FIXED_GAIN_G 0x1441 1149 #define ADC_YPBPR_FIXED_GAIN_B 0x14B7 1150 #define ADC_YPBPR_FIXED_OFFSET_R 0x0800 1151 #define ADC_YPBPR_FIXED_OFFSET_G 0x0100 1152 #define ADC_YPBPR_FIXED_OFFSET_B 0x0800 1153 #define ADC_SCART_FIXED_GAIN_R 0x1796 1154 #define ADC_SCART_FIXED_GAIN_G 0x1796 1155 #define ADC_SCART_FIXED_GAIN_B 0x1796 1156 #define ADC_SCART_FIXED_OFFSET_R 0x0000 1157 #define ADC_SCART_FIXED_OFFSET_G 0x0000 1158 #define ADC_SCART_FIXED_OFFSET_B 0x0000 1159 1160 #define SUPPORT_DUAL_MIU // Manhattan dual_MIU is not work now, RD is checking, disable dual_MIU first 1161 #define SUPPORT_SC0_SUB_WIN FALSE 1162 #define SUPPORT_DUAL_MIU_MIRROR_SWAP_IPM TRUE 1163 // IP Authorization number for dolby 1164 #define IPAUTH_DOLBY_HDR_PIN 118 1165 #endif /* MHAL_XC_CONFIG_H */ 1166 1167