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Searched refs:OFFSET_R2_TO_COMM_DDR (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/audio/hal/k6lite/audio/
H A DdecR2_proj.h171 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
180 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
181 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
193 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
197 #define PCMR_EVO_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DDPENC_METADATA_DRAM_ADDR)
200 #define DEC1_METADATA1_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DEC1_METADATA1_DRAM_ADDR)
201 #define DEC1_METADATA2_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DEC1_METADATA2_DRAM_ADDR)
202 #define DEC1_METADATA3_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DEC1_METADATA3_DRAM_ADDR)
204 #define DEC2_METADATA1_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DEC2_METADATA1_DRAM_ADDR)
205 #define DEC2_METADATA2_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DEC2_METADATA2_DRAM_ADDR)
[all …]
H A DsndR2_proj.h72 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
81 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
82 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
94 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
116 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
/utopia/UTPA2-700.0.x/modules/audio/hal/curry/audio/
H A DdecR2_proj.h171 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
180 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
181 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
193 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
197 #define PCMR_EVO_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DDPENC_METADATA_DRAM_ADDR)
200 #define DEC1_METADATA1_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DEC1_METADATA1_DRAM_ADDR)
201 #define DEC1_METADATA2_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DEC1_METADATA2_DRAM_ADDR)
202 #define DEC1_METADATA3_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DEC1_METADATA3_DRAM_ADDR)
204 #define DEC2_METADATA1_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DEC2_METADATA1_DRAM_ADDR)
205 #define DEC2_METADATA2_BUF (OFFSET_R2_TO_COMM_DDR + OFFSET_DEC2_METADATA2_DRAM_ADDR)
[all …]
H A DsndR2_proj.h84 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
93 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
94 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
106 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
149 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
/utopia/UTPA2-700.0.x/modules/audio/hal/mustang/audio/
H A DsndR2_proj.h83 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
92 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
93 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
99 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
105 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
127 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
131 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
148 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
H A DdecR2_proj.h158 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
174 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
175 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
181 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
187 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
202 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
/utopia/UTPA2-700.0.x/modules/audio/hal/maserati/audio/
H A DsndR2_proj.h66 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
75 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
76 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
82 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
88 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
110 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
114 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
131 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
H A DdecR2_proj.h149 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
165 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
166 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
172 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
178 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
193 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
/utopia/UTPA2-700.0.x/modules/audio/hal/macan/audio/
H A DsndR2_proj.h83 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
92 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
93 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
99 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
105 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
127 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
131 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
148 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
H A DdecR2_proj.h158 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
174 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
175 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
181 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
187 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
202 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
/utopia/UTPA2-700.0.x/modules/audio/hal/M7821/audio/
H A DsndR2_proj.h64 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
73 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
74 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
80 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
86 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
108 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
112 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
129 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
H A DdecR2_proj.h145 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
161 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
162 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
168 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
174 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
189 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
/utopia/UTPA2-700.0.x/modules/audio/hal/M7621/audio/
H A DsndR2_proj.h83 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
92 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
93 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
99 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
105 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
127 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
131 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
148 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
H A DdecR2_proj.h158 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
174 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
175 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
181 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
187 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
202 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
/utopia/UTPA2-700.0.x/modules/audio/hal/maxim/audio/
H A DsndR2_proj.h83 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
92 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
93 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
99 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
105 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
127 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
131 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
148 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
H A DdecR2_proj.h158 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
174 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
175 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
181 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
187 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
202 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
/utopia/UTPA2-700.0.x/modules/audio/hal/manhattan/audio/
H A DsndR2_proj.h56 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
65 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
66 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
72 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
78 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
93 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
105 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
H A DdecR2_proj.h119 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
128 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
129 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
135 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET)
141 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
148 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET)
/utopia/UTPA2-700.0.x/modules/audio/hal/k6/audio/
H A DsndR2_proj.h84 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
93 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
94 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
106 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
149 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
150 #define MPEG_ENC2_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC2_DRAM_BASE)
153 #define MPEG_ENC_APTS_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_APTS_DRAM_BASE)
H A DdecR2_proj.h188 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
204 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
205 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
217 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
241 #define MPEG_ENC_APTS_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_APTS_DRAM_BASE)
/utopia/UTPA2-700.0.x/modules/audio/hal/kano/audio/
H A DsndR2_proj.h84 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) macro
93 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
94 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
106 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
149 #define MPEG_ENC_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_DRAM_BASE)
150 #define MPEG_ENC2_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC2_DRAM_BASE)
153 #define MPEG_ENC_APTS_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_APTS_DRAM_BASE)
H A DdecR2_proj.h188 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
204 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
205 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
217 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
241 #define MPEG_ENC_APTS_BASE (OFFSET_R2_TO_COMM_DDR+ OFFSET_MP3_ENC_APTS_DRAM_BASE)
/utopia/UTPA2-700.0.x/modules/audio/hal/maldives/audio/
H A DdecR2_proj.h149 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
158 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
159 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
171 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)
/utopia/UTPA2-700.0.x/modules/audio/hal/mooney/audio/
H A DdecR2_proj.h149 …#define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_S… macro
158 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR)
159 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR)
171 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET)