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Searched refs:MSK_UD7_STATE (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c180 #define MSK_UD7_STATE 0x0C macro
3822 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
3838 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
3840 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
3856 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c179 #define MSK_UD7_STATE 0x0C macro
7184 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
7200 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7202 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
7218 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c185 #define MSK_UD7_STATE 0x0C macro
7310 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7328 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c185 #define MSK_UD7_STATE 0x0C macro
7310 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7328 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c184 #define MSK_UD7_STATE 0x0C macro
7257 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
7273 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7275 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
7291 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c185 #define MSK_UD7_STATE 0x0C macro
7310 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7328 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c179 #define MSK_UD7_STATE 0x0C macro
7184 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
7200 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7202 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
7218 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c180 #define MSK_UD7_STATE 0x0C macro
3822 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
3838 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
3840 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
3856 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c185 #define MSK_UD7_STATE 0x0C macro
7310 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7328 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c185 #define MSK_UD7_STATE 0x0C macro
7310 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
7326 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7328 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
7344 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c179 #define MSK_UD7_STATE 0x0C macro
3821 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
3837 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
3839 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
3855 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c179 #define MSK_UD7_STATE 0x0C macro
7200 if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_WRITE ) // write enable in HAL_AVD_AFEC_SetRegFromDSP()
7216 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_FREE, MSK_UD7_STATE); in HAL_AVD_AFEC_SetRegFromDSP()
7218 else if( ( u8Ctl & MSK_UD7_STATE ) == VAL_UD7_READ ) in HAL_AVD_AFEC_SetRegFromDSP()
7234 RIU_WriteByteMask( BK_AFEC_DC, VAL_UD7_READ_END, MSK_UD7_STATE ); in HAL_AVD_AFEC_SetRegFromDSP()