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Searched refs:MIU1_REG_BASE2 (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/mvd_lite/
H A DregMVD_EX.h116 #define MIU1_REG_BASE2 (0x62200) macro
157 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2+((0x0003)<<1))
158 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2+((0x0003)<<1)+1)
159 #define MIU1_RQ5_MASK_L (MIU1_REG_BASE2+((0x0013)<<1))
160 #define MIU1_RQ5_MASK_H (MIU1_REG_BASE2+((0x0013)<<1)+1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/mvd_v3/
H A DregMVD_EX.h117 #define MIU1_REG_BASE2 0x62200UL macro
148 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2 + 0x0003*2)
149 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2 + 0x0003*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/mvd_v3/
H A DregMVD_EX.h117 #define MIU1_REG_BASE2 0x62200UL macro
148 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2 + 0x0003*2)
149 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2 + 0x0003*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/mvd_v3/
H A DregMVD_EX.h117 #define MIU1_REG_BASE2 0x62200UL macro
148 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2 + 0x0003*2)
149 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2 + 0x0003*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/mvd_v3/
H A DregMVD_EX.h117 #define MIU1_REG_BASE2 0x62200UL macro
150 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2 + 0x0003*2)
151 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2 + 0x0003*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/mvd_v3/
H A DregMVD_EX.h118 #define MIU1_REG_BASE2 0x62200UL macro
150 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2 + 0x0003*2)
151 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2 + 0x0003*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/mvd_v3/
H A DregMVD_EX.h118 #define MIU1_REG_BASE2 0x62200UL macro
150 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2 + 0x0003*2)
151 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2 + 0x0003*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/mvd_v3/
H A DregMVD_EX.h118 #define MIU1_REG_BASE2 0x62200UL macro
150 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2 + 0x0003*2)
151 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2 + 0x0003*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/mvd_v3/
H A DregMVD_EX.h118 #define MIU1_REG_BASE2 0x62200UL macro
150 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2 + 0x0003*2)
151 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2 + 0x0003*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/mvd_v3/
H A DregMVD_EX.h118 #define MIU1_REG_BASE2 0x62200UL macro
150 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2 + 0x0003*2)
151 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2 + 0x0003*2 +1)